4f04db4b54
Along the lines of D77454 and D79968. Unlike loads and stores, the default alignment is getPrefTypeAlign, to match the existing handling in various places, including SelectionDAG and InstCombine. Differential Revision: https://reviews.llvm.org/D80044
30 lines
1.4 KiB
LLVM
30 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -sroa -S | FileCheck %s
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target datalayout = "e-p:64:64:64:32"
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%struct.test = type { %struct.basic, %struct.basic }
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%struct.basic = type { i16, i8 }
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define i16 @test(%struct.test* %ts2.i) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[S_SROA_0:%.*]] = alloca [3 x i8], align 8
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; CHECK-NEXT: [[S_SROA_0_0__SROA_CAST:%.*]] = bitcast %struct.test* [[TS2_I:%.*]] to i8*
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; CHECK-NEXT: [[S_SROA_0_0__SROA_IDX:%.*]] = getelementptr inbounds [3 x i8], [3 x i8]* [[S_SROA_0]], i32 0, i32 0
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; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 [[S_SROA_0_0__SROA_CAST]], i8* align 8 [[S_SROA_0_0__SROA_IDX]], i32 3, i1 false)
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; CHECK-NEXT: [[X1_I_I:%.*]] = getelementptr inbounds [[STRUCT_TEST:%.*]], %struct.test* [[TS2_I]], i32 0, i32 0, i32 0
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; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[X1_I_I]]
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; CHECK-NEXT: ret i16 [[TMP0]]
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;
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entry:
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%s = alloca %struct.test
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%0 = bitcast %struct.test* %ts2.i to i8*
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%1 = bitcast %struct.test* %s to i8*
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 3, i1 false)
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%x1.i.i = getelementptr inbounds %struct.test, %struct.test* %ts2.i, i32 0, i32 0, i32 0
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%2 = load i16, i16* %x1.i.i
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ret i16 %2
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}
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1)
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