8bde5e58c0
The delayed stack protector feature which is currently used for SDAG (and thus allows for more commonly generating tail calls) depends on being able to extract the tail call into a separate return block. To do this it also has to extract the vreg->physreg copies that set up the call's arguments, since if it doesn't then the call inst ends up using undefined physregs in it's new spliced block. SelectionDAG implementations can do this because they delay emitting register copies until *after* the stack arguments are set up. GISel however just processes and emits the arguments in IR order, so stack arguments always end up last, and thus this breaks the code that looks for any register arg copies that precede the call instruction. This patch adds a thunk argument to the assignValueToReg() and custom assignment hooks. For outgoing arguments, register assignments use this return param to return a thunk that does the actual generating of the copies. We collect these until all the outgoing stack assignments have been done and then execute them, so that the copies (and perhaps some artifacts like G_SEXTs) are placed after any stores. Differential Revision: https://reviews.llvm.org/D110610
124 lines
4.9 KiB
C++
124 lines
4.9 KiB
C++
//===-- PPCCallLowering.h - Call lowering for GlobalISel -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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///
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//===----------------------------------------------------------------------===//
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#include "PPCCallLowering.h"
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#include "PPCISelLowering.h"
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#include "PPCSubtarget.h"
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#include "PPCTargetMachine.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/TargetCallingConv.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "ppc-call-lowering"
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using namespace llvm;
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PPCCallLowering::PPCCallLowering(const PPCTargetLowering &TLI)
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: CallLowering(&TLI) {}
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bool PPCCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, ArrayRef<Register> VRegs,
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FunctionLoweringInfo &FLI,
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Register SwiftErrorVReg) const {
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assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
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"Return value without a vreg");
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if (VRegs.size() > 0)
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return false;
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MIRBuilder.buildInstr(PPC::BLR8);
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return true;
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}
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bool PPCCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const {
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return false;
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}
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bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const auto &DL = F.getParent()->getDataLayout();
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auto &TLI = *getTLI<PPCTargetLowering>();
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// Loop over each arg, set flags and split to single value types
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SmallVector<ArgInfo, 8> SplitArgs;
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unsigned I = 0;
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for (const auto &Arg : F.args()) {
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if (DL.getTypeStoreSize(Arg.getType()).isZero())
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continue;
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ArgInfo OrigArg{VRegs[I], Arg, I};
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setArgFlags(OrigArg, I + AttributeList::FirstArgIndex, DL, F);
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splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
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++I;
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}
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CCAssignFn *AssignFn =
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TLI.ccAssignFnForCall(F.getCallingConv(), false, F.isVarArg());
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IncomingValueAssigner ArgAssigner(AssignFn);
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FormalArgHandler ArgHandler(MIRBuilder, MRI);
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return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
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MIRBuilder, F.getCallingConv(),
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F.isVarArg());
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}
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void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
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Register PhysReg,
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CCValAssign VA) {
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markPhysRegUsed(PhysReg);
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IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
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}
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void PPCIncomingValueHandler::assignValueToAddress(Register ValVReg,
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Register Addr, LLT MemTy,
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MachinePointerInfo &MPO,
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CCValAssign &VA) {
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// define a lambda expression to load value
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auto BuildLoad = [](MachineIRBuilder &MIRBuilder, MachinePointerInfo &MPO,
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LLT MemTy, const DstOp &Res, Register Addr) {
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MachineFunction &MF = MIRBuilder.getMF();
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auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
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inferAlignFromPtrInfo(MF, MPO));
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return MIRBuilder.buildLoad(Res, Addr, *MMO);
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};
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BuildLoad(MIRBuilder, MPO, MemTy, ValVReg, Addr);
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}
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Register PPCIncomingValueHandler::getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) {
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auto &MFI = MIRBuilder.getMF().getFrameInfo();
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const bool IsImmutable = !Flags.isByVal();
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int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
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MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
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// Build Frame Index based on whether the machine is 32-bit or 64-bit
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llvm::LLT FramePtr = LLT::pointer(
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0, MIRBuilder.getMF().getDataLayout().getPointerSizeInBits());
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MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI);
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StackUsed = std::max(StackUsed, Size + Offset);
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return AddrReg.getReg(0);
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}
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void FormalArgHandler::markPhysRegUsed(unsigned PhysReg) {
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MIRBuilder.getMRI()->addLiveIn(PhysReg);
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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}
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