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clang-p2996/llvm/lib/Target/RISCV
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Liqin Weng 92153a9aa7 [RISCV] Support immediate vtype of VSETVLI/VSETIVLI in asm parser 
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D115133
2022-01-07 02:26:41 +00:00
..
AsmParser
[RISCV] Support immediate vtype of VSETVLI/VSETIVLI in asm parser
2022-01-07 02:26:41 +00:00
Disassembler
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
MCTargetDesc
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
CMakeLists.txt
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCV.h
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCV.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVAsmPrinter.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
Revert "[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos"
2021-10-02 10:44:11 -07:00
RISCVFrameLowering.cpp
[RISCV] Fix a bug in RISCVFrameLowering.
2021-11-30 10:39:35 +08:00
RISCVFrameLowering.h
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
RISCVGatherScatterLowering.cpp
[RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values.
2022-01-04 10:13:34 -08:00
RISCVInsertVSETVLI.cpp
[RISCV] Prune unnecessary vector pseudo instructions. NFC
2022-01-01 19:53:53 -08:00
RISCVInstrFormats.td
[RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.
2021-12-14 10:17:57 -08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp
[RISCV] Prune more unnecessary vector pseudo instructions. NFC
2022-01-02 23:00:42 -08:00
RISCVInstrInfo.h
[RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.
2021-12-14 10:17:57 -08:00
RISCVInstrInfo.td
[RISCV] Support named opcodes in .insn directive.
2021-12-13 20:59:33 -08:00
RISCVInstrInfoA.td
…
RISCVInstrInfoC.td
[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td
[RISCV] Change RISCVISD::FCVT*RTZ opcodes to take rounding mode as an operand.
2022-01-06 08:12:12 -08:00
RISCVInstrInfoF.td
[RISCV] Change RISCVISD::FCVT*RTZ opcodes to take rounding mode as an operand.
2022-01-06 08:12:12 -08:00
RISCVInstrInfoM.td
[RISCV] Use MULHU for more division by constant cases.
2021-12-09 09:10:14 -08:00
RISCVInstrInfoV.td
[RISCV] Support immediate vtype of VSETVLI/VSETIVLI in asm parser
2022-01-07 02:26:41 +00:00
RISCVInstrInfoVPseudos.td
[RISCV] Support immediate vtype of VSETVLI/VSETIVLI in asm parser
2022-01-07 02:26:41 +00:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Use vmv.s.x instead of vfmv.s.f when the floating point scalar is 0.
2021-12-30 10:16:54 +08:00
RISCVInstrInfoZb.td
[RISCV] Fold (and (not (srl X, C)), 1) to (xor (bexti X, C), 1) when have Zbs extension.
2021-12-16 15:01:05 +08:00
RISCVInstrInfoZfh.td
[RISCV] Change RISCVISD::FCVT*RTZ opcodes to take rounding mode as an operand.
2022-01-06 08:12:12 -08:00
RISCVInstructionSelector.cpp
Revert "[llvm] Remove redundant member initialization (NFC)"
2022-01-03 11:28:47 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Use macros to reduce repetive switch cases. NFC
2022-01-05 09:00:48 -08:00
RISCVISelDAGToDAG.h
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
RISCVISelLowering.cpp
[RISCV] Don't advertise i32->i64 zextload as free for RV64.
2022-01-06 08:13:42 -08:00
RISCVISelLowering.h
[RISCV] Change RISCVISD::FCVT*RTZ opcodes to take rounding mode as an operand.
2022-01-06 08:12:12 -08:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
…
RISCVMCInstLower.cpp
…
RISCVMergeBaseOffset.cpp
[RISCV] Remove unused member variable. NFC
2021-10-14 12:56:47 -07:00
RISCVRegisterBankInfo.cpp
Revert "[llvm] Remove redundant member initialization (NFC)"
2022-01-03 11:28:47 -08:00
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Remove FCSR from RISCVRegisterInfo.
2021-12-10 09:24:13 -08:00
RISCVRegisterInfo.h
[RISCV] Emit DWARF location expression for RVV stack objects.
2021-11-27 15:13:10 +08:00
RISCVRegisterInfo.td
[RISCV] Remove FCSR from RISCVRegisterInfo.
2021-12-10 09:24:13 -08:00
RISCVSchedRocket.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVSchedSiFive7.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVSchedule.td
…
RISCVScheduleB.td
…
RISCVScheduleV.td
…
RISCVSExtWRemoval.cpp
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCVSubtarget.cpp
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
RISCVSubtarget.h
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
RISCVSystemOperands.td
[RISCV] Emit DWARF location expression for RVV stack objects.
2021-11-27 15:13:10 +08:00
RISCVTargetMachine.cpp
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add target specific loop unrolling and peeling preferences
2021-12-18 12:54:50 -08:00
RISCVTargetTransformInfo.h
[RISCV] Disable interleaving scalar loops in the loop vectorizer.
2021-12-23 08:37:24 -06:00