da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
227 lines
8.1 KiB
LLVM
227 lines
8.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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; Test the localizer did something and we don't materialize all
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; constants in SGPRs in the entry block.
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define amdgpu_kernel void @localize_constants(i1 %cond) {
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; GFX9-LABEL: localize_constants:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0
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; GFX9-NEXT: s_mov_b32 s0, -1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_xor_b32 s1, s1, -1
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; GFX9-NEXT: s_and_b32 s1, s1, 1
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; GFX9-NEXT: s_cmp_lg_u32 s1, 0
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; GFX9-NEXT: s_cbranch_scc0 .LBB0_2
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; GFX9-NEXT: ; %bb.1: ; %bb1
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b
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; GFX9-NEXT: s_mov_b32 s0, 0
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: .LBB0_2: ; %Flow
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; GFX9-NEXT: s_xor_b32 s0, s0, -1
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; GFX9-NEXT: s_and_b32 s0, s0, 1
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; GFX9-NEXT: s_cmp_lg_u32 s0, 0
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; GFX9-NEXT: s_cbranch_scc1 .LBB0_4
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; GFX9-NEXT: ; %bb.3: ; %bb0
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: .LBB0_4: ; %bb2
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; GFX9-NEXT: s_endpgm
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entry:
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br i1 %cond, label %bb0, label %bb1
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bb0:
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store volatile i32 123, i32 addrspace(1)* undef
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store volatile i32 456, i32 addrspace(1)* undef
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store volatile i32 999, i32 addrspace(1)* undef
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store volatile i32 1000, i32 addrspace(1)* undef
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store volatile i32 455, i32 addrspace(1)* undef
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store volatile i32 23526, i32 addrspace(1)* undef
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br label %bb2
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bb1:
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store volatile i32 23526, i32 addrspace(1)* undef
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store volatile i32 455, i32 addrspace(1)* undef
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store volatile i32 1000, i32 addrspace(1)* undef
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store volatile i32 456, i32 addrspace(1)* undef
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store volatile i32 999, i32 addrspace(1)* undef
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store volatile i32 123, i32 addrspace(1)* undef
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br label %bb2
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bb2:
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ret void
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}
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; FIXME: These aren't localized because thesee were legalized before
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; the localizer, and are no longer G_GLOBAL_VALUE.
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@gv0 = addrspace(1) global i32 undef, align 4
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@gv1 = addrspace(1) global i32 undef, align 4
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@gv2 = addrspace(1) global i32 undef, align 4
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@gv3 = addrspace(1) global i32 undef, align 4
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define amdgpu_kernel void @localize_globals(i1 %cond) {
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; GFX9-LABEL: localize_globals:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0
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; GFX9-NEXT: s_mov_b32 s0, -1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_xor_b32 s1, s1, -1
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; GFX9-NEXT: s_and_b32 s1, s1, 1
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; GFX9-NEXT: s_cmp_lg_u32 s1, 0
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; GFX9-NEXT: s_cbranch_scc0 .LBB1_2
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; GFX9-NEXT: ; %bb.1: ; %bb1
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; GFX9-NEXT: s_getpc_b64 s[0:1]
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; GFX9-NEXT: s_add_u32 s0, s0, gv2@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s1, s1, gv2@gotpcrel32@hi+12
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; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
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; GFX9-NEXT: s_getpc_b64 s[0:1]
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; GFX9-NEXT: s_add_u32 s0, s0, gv3@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s1, s1, gv3@gotpcrel32@hi+12
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; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: v_mov_b32_e32 v1, 1
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; GFX9-NEXT: s_mov_b32 s0, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_store_dword v0, v0, s[2:3]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: .LBB1_2: ; %Flow
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; GFX9-NEXT: s_xor_b32 s0, s0, -1
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; GFX9-NEXT: s_and_b32 s0, s0, 1
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; GFX9-NEXT: s_cmp_lg_u32 s0, 0
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; GFX9-NEXT: s_cbranch_scc1 .LBB1_4
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; GFX9-NEXT: ; %bb.3: ; %bb0
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; GFX9-NEXT: s_getpc_b64 s[0:1]
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; GFX9-NEXT: s_add_u32 s0, s0, gv0@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s1, s1, gv0@gotpcrel32@hi+12
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
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; GFX9-NEXT: s_getpc_b64 s[2:3]
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; GFX9-NEXT: s_add_u32 s2, s2, gv1@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s3, s3, gv1@gotpcrel32@hi+12
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; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: v_mov_b32_e32 v1, 1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_store_dword v0, v0, s[0:1]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: .LBB1_4: ; %bb2
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; GFX9-NEXT: s_endpgm
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entry:
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br i1 %cond, label %bb0, label %bb1
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bb0:
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store volatile i32 0, i32 addrspace(1)* @gv0
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store volatile i32 1, i32 addrspace(1)* @gv1
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br label %bb2
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bb1:
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store volatile i32 0, i32 addrspace(1)* @gv2
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store volatile i32 1, i32 addrspace(1)* @gv3
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br label %bb2
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bb2:
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ret void
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}
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@static.gv0 = internal addrspace(1) global i32 undef, align 4
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@static.gv1 = internal addrspace(1) global i32 undef, align 4
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@static.gv2 = internal addrspace(1) global i32 undef, align 4
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@static.gv3 = internal addrspace(1) global i32 undef, align 4
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define void @localize_internal_globals(i1 %cond) {
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; GFX9-LABEL: localize_internal_globals:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
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; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; GFX9-NEXT: s_xor_b64 s[4:5], vcc, -1
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; GFX9-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
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; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7]
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; GFX9-NEXT: s_cbranch_execz .LBB2_2
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; GFX9-NEXT: ; %bb.1: ; %bb1
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; GFX9-NEXT: s_getpc_b64 s[6:7]
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; GFX9-NEXT: s_add_u32 s6, s6, static.gv2@rel32@lo+4
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; GFX9-NEXT: s_addc_u32 s7, s7, static.gv2@rel32@hi+12
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: global_store_dword v0, v0, s[6:7]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_getpc_b64 s[6:7]
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; GFX9-NEXT: s_add_u32 s6, s6, static.gv3@rel32@lo+4
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; GFX9-NEXT: s_addc_u32 s7, s7, static.gv3@rel32@hi+12
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; GFX9-NEXT: v_mov_b32_e32 v1, 1
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; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: .LBB2_2: ; %Flow
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; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
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; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
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; GFX9-NEXT: s_cbranch_execz .LBB2_4
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; GFX9-NEXT: ; %bb.3: ; %bb0
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; GFX9-NEXT: s_getpc_b64 s[6:7]
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; GFX9-NEXT: s_add_u32 s6, s6, static.gv0@rel32@lo+4
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; GFX9-NEXT: s_addc_u32 s7, s7, static.gv0@rel32@hi+12
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: global_store_dword v0, v0, s[6:7]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_getpc_b64 s[6:7]
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; GFX9-NEXT: s_add_u32 s6, s6, static.gv1@rel32@lo+4
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; GFX9-NEXT: s_addc_u32 s7, s7, static.gv1@rel32@hi+12
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; GFX9-NEXT: v_mov_b32_e32 v1, 1
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; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: .LBB2_4: ; %bb2
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; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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entry:
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br i1 %cond, label %bb0, label %bb1
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bb0:
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store volatile i32 0, i32 addrspace(1)* @static.gv0
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store volatile i32 1, i32 addrspace(1)* @static.gv1
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br label %bb2
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bb1:
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store volatile i32 0, i32 addrspace(1)* @static.gv2
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store volatile i32 1, i32 addrspace(1)* @static.gv3
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br label %bb2
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bb2:
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ret void
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}
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