da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
104 lines
3.9 KiB
LLVM
104 lines
3.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefixes=ALL-ASM,OSABI-AMDHSA-ASM %s
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; RUN: llc -filetype=obj -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | llvm-readelf -S -r -s --notes - | FileCheck --check-prefix=OSABI-AMDHSA-ELF %s
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; ALL-ASM-LABEL: {{^}}fadd:
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; OSABI-AMDHSA-ASM-NOT: .hsa_code_object_version
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; OSABI-AMDHSA-ASM-NOT: .hsa_code_object_isa
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; OSABI-AMDHSA-ASM-NOT: .amdgpu_hsa_kernel
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; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t
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; OSABI-AMDHSA-ASM: s_endpgm
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; OSABI-AMDHSA-ASM: .section .rodata,#alloc
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; OSABI-AMDHSA-ASM: .p2align 6
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; OSABI-AMDHSA-ASM: .amdhsa_kernel fadd
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; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_private_segment_buffer 1
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; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_kernarg_segment_ptr 1
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; OSABI-AMDHSA-ASM: .amdhsa_next_free_vgpr 3
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; OSABI-AMDHSA-ASM: .amdhsa_next_free_sgpr 8
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; OSABI-AMDHSA-ASM: .amdhsa_reserve_vcc 0
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; OSABI-AMDHSA-ASM: .amdhsa_reserve_flat_scratch 0
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; OSABI-AMDHSA-ASM: .end_amdhsa_kernel
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; OSABI-AMDHSA-ASM: .text
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; ALL-ASM-LABEL: {{^}}fsub:
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; OSABI-AMDHSA-ASM-NOT: .amdgpu_hsa_kernel
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; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t
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; OSABI-AMDHSA-ASM: s_endpgm
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; OSABI-AMDHSA-ASM: .section .rodata,#alloc
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; OSABI-AMDHSA-ASM: .p2align 6
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; OSABI-AMDHSA-ASM: .amdhsa_kernel fsub
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; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_private_segment_buffer 1
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; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_kernarg_segment_ptr 1
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; OSABI-AMDHSA-ASM: .amdhsa_next_free_vgpr 3
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; OSABI-AMDHSA-ASM: .amdhsa_next_free_sgpr 8
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; OSABI-AMDHSA-ASM: .amdhsa_reserve_vcc 0
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; OSABI-AMDHSA-ASM: .amdhsa_reserve_flat_scratch 0
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; OSABI-AMDHSA-ASM: .end_amdhsa_kernel
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; OSABI-AMDHSA-ASM: .text
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; OSABI-AMDHSA-ASM-NOT: .hsa_code_object_version
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; OSABI-AMDHSA-ASM-NOT: .hsa_code_object_isa
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; OSABI-AMDHSA-ASM-NOT: .amd_amdgpu_isa
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; OSABI-AMDHSA-ASM-NOT: .amd_amdgpu_hsa_metadata
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; OSABI-AMDHSA-ASM-NOT: .amd_amdgpu_pal_metadata
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; OSABI-AMDHSA-ELF: Section Headers
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; OSABI-AMDHSA-ELF: .text PROGBITS {{[0-9]+}} {{[0-9]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256
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; OSABI-AMDHSA-ELF: .rodata PROGBITS {{[0-9]+}} {{[0-9]+}} {{[0-9a-f]+}} {{[0-9]+}} A {{[0-9]+}} {{[0-9]+}} 64
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; OSABI-AMDHSA-ELF: Relocation section '.rela.rodata' at offset
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; OSABI-AMDHSA-ELF: R_AMDGPU_REL64 0000000000000000 fadd + 10
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; OSABI-AMDHSA-ELF: R_AMDGPU_REL64 0000000000000100 fsub + 10
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; OSABI-AMDHSA-ELF: R_AMDGPU_REL64 0000000000000200 empty + 10
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; OSABI-AMDHSA-ELF: Symbol table '.symtab' contains {{[0-9]+}} entries
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; OSABI-AMDHSA-ELF: {{[0-9]+}}: 0000000000000000 {{[0-9]+}} FUNC GLOBAL PROTECTED {{[0-9]+}} fadd
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; OSABI-AMDHSA-ELF: {{[0-9]+}}: 0000000000000000 64 OBJECT GLOBAL DEFAULT {{[0-9]+}} fadd.kd
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; OSABI-AMDHSA-ELF: {{[0-9]+}}: 0000000000000100 {{[0-9]+}} FUNC GLOBAL PROTECTED {{[0-9]+}} fsub
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; OSABI-AMDHSA-ELF: {{[0-9]+}}: 0000000000000040 64 OBJECT GLOBAL DEFAULT {{[0-9]+}} fsub.kd
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; OSABI-AMDHSA-ELF: Displaying notes found in: .note
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; OSABI-AMDHSA-ELF: AMDGPU 0x{{[0-9a-f]+}} NT_AMDGPU_METADATA (AMDGPU Metadata)
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define amdgpu_kernel void @fadd(
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float addrspace(1)* %r,
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float addrspace(1)* %a,
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float addrspace(1)* %b) {
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entry:
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%a.val = load float, float addrspace(1)* %a
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%b.val = load float, float addrspace(1)* %b
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%r.val = fadd float %a.val, %b.val
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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define amdgpu_kernel void @fsub(
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float addrspace(1)* %r,
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float addrspace(1)* %a,
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float addrspace(1)* %b) {
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entry:
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%a.val = load float, float addrspace(1)* %a
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%b.val = load float, float addrspace(1)* %b
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%r.val = fsub float %a.val, %b.val
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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; Make sure kernel arguments do not count towards the number of
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; registers used.
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;
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; ALL-ASM-LABEL: {{^}}empty:
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; ALL-ASM: .amdhsa_next_free_vgpr 1
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; ALL-ASM: .amdhsa_next_free_sgpr 1
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define amdgpu_kernel void @empty(
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i32 %i,
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float addrspace(1)* %r,
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float addrspace(1)* %a,
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float addrspace(1)* %b) {
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entry:
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ret void
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}
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