da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
30 lines
1.1 KiB
LLVM
30 lines
1.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
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@ptr_load = addrspace(3) global i32 addrspace(4)* undef, align 8
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; Make sure when the load from %ptr2 is folded the chain isn't lost,
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; resulting in losing the store to gptr
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; FUNC-LABEL: {{^}}missing_store_reduced:
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; SI: s_load_dwordx4
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; SI-DAG: ds_read_b64
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; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
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; SI-DAG: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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; SI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}
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; SI-DAG: buffer_store_dword
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; SI-DAG: buffer_store_dword
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; SI: s_endpgm
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define amdgpu_kernel void @missing_store_reduced(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @ptr_load, align 8
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%ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 2
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store i32 99, i32 addrspace(1)* %gptr, align 4
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%tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
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store i32 %tmp2, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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