da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
92 lines
3.2 KiB
LLVM
Executable File
92 lines
3.2 KiB
LLVM
Executable File
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
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define amdgpu_kernel void @sext_i16_to_i32_uniform(i32 addrspace(1)* %out, i16 %a, i32 %b) {
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; GCN-LABEL: sext_i16_to_i32_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_sext_i32_i16 s4, s4
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; GCN-NEXT: s_add_i32 s4, s5, s4
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%sext = sext i16 %a to i32
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%res = add i32 %b, %sext
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sext_i16_to_i64_uniform(i64 addrspace(1)* %out, i16 %a, i64 %b) {
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; GCN-LABEL: sext_i16_to_i64_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
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; GCN-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0xd
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
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; GCN-NEXT: s_add_u32 s4, s6, s4
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; GCN-NEXT: s_addc_u32 s5, s7, s5
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%sext = sext i16 %a to i64
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%res = add i64 %b, %sext
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store i64 %res, i64 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sext_i16_to_i32_divergent(i32 addrspace(1)* %out, i16 %a, i32 %b) {
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; GCN-LABEL: sext_i16_to_i32_divergent:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.truncated = trunc i32 %tid to i16
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%divergent.a = add i16 %a, %tid.truncated
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%sext = sext i16 %divergent.a to i32
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store i32 %sext, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sext_i16_to_i64_divergent(i64 addrspace(1)* %out, i16 %a, i64 %b) {
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; GCN-LABEL: sext_i16_to_i64_divergent:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.truncated = trunc i32 %tid to i16
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%divergent.a = add i16 %a, %tid.truncated
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%sext = sext i16 %divergent.a to i64
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store i64 %sext, i64 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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