da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
242 lines
9.4 KiB
LLVM
242 lines
9.4 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone speculatable
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; GCN-LABEL: {{^}}s_sub_i32:
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; GCN: s_load_dwordx2 s{{\[}}[[A:[0-9]+]]:[[B:[0-9]+]]{{\]}}
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; GCN: s_load_dwordx2
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; GCN: s_sub_i32 s{{[0-9]+}}, s[[A]], s[[B]]
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define amdgpu_kernel void @s_sub_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%result = sub i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_sub_imm_i32:
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; GCN: s_load_dword [[A:s[0-9]+]]
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; GCN: s_sub_i32 s{{[0-9]+}}, 0x4d2, [[A]]
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define amdgpu_kernel void @s_sub_imm_i32(i32 addrspace(1)* %out, i32 %a) {
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%result = sub i32 1234, %a
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_i32:
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; SI: v_subrev_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @test_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
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%a = load i32, i32 addrspace(1)* %in
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%b = load i32, i32 addrspace(1)* %b_ptr
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%result = sub i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_imm_i32:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, 0x7b, v{{[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+}}, 0x7b, v{{[0-9]+}}
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define amdgpu_kernel void @test_sub_imm_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%a = load i32, i32 addrspace(1)* %in
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%result = sub i32 123, %a
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_v2i32:
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @test_sub_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%result = sub <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_v4i32:
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @test_sub_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%result = sub <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_i16:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; GFX89: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @test_sub_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i16, i16 addrspace(1)* %in, i32 %tid
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%b_ptr = getelementptr i16, i16 addrspace(1)* %gep, i32 1
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%a = load volatile i16, i16 addrspace(1)* %gep
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%b = load volatile i16, i16 addrspace(1)* %b_ptr
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%result = sub i16 %a, %b
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store i16 %result, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_v2i16:
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; VI: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_sub_u16_sdwa v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_pk_sub_i16
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define amdgpu_kernel void @test_sub_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in, i32 %tid
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%b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %gep, i16 1
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%a = load <2 x i16>, <2 x i16> addrspace(1)* %gep
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%b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
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%result = sub <2 x i16> %a, %b
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store <2 x i16> %result, <2 x i16> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_v4i16:
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; VI: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_sub_u16_sdwa v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; VI: v_sub_u16_sdwa v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX9: v_pk_sub_i16
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; GFX9: v_pk_sub_i16
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define amdgpu_kernel void @test_sub_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in, i32 %tid
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%b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %gep, i16 1
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%a = load <4 x i16>, <4 x i16> addrspace(1) * %gep
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%b = load <4 x i16>, <4 x i16> addrspace(1) * %b_ptr
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%result = sub <4 x i16> %a, %b
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store <4 x i16> %result, <4 x i16> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_sub_i64:
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; GCN: s_sub_u32
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; GCN: s_subb_u32
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define amdgpu_kernel void @s_sub_i64(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) nounwind {
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%result = sub i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}v_sub_i64:
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; SI: v_sub_i32_e32
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; SI: v_subb_u32_e32
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; VI: v_sub_u32_e32
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; VI: v_subb_u32_e32
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; GFX9: v_sub_co_u32_e32
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; GFX9: v_subb_co_u32_e32
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define amdgpu_kernel void @v_sub_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%a_ptr = getelementptr i64, i64 addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr i64, i64 addrspace(1)* %inB, i32 %tid
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%a = load i64, i64 addrspace(1)* %a_ptr
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%b = load i64, i64 addrspace(1)* %b_ptr
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%result = sub i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}v_test_sub_v2i64:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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define amdgpu_kernel void @v_test_sub_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%a_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inB, i32 %tid
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%a = load <2 x i64>, <2 x i64> addrspace(1)* %a_ptr
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%b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
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%result = sub <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_test_sub_v4i64:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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define amdgpu_kernel void @v_test_sub_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* noalias %inA, <4 x i64> addrspace(1)* noalias %inB) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%a_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %inB, i32 %tid
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%a = load <4 x i64>, <4 x i64> addrspace(1)* %a_ptr
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%b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
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%result = sub <4 x i64> %a, %b
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store <4 x i64> %result, <4 x i64> addrspace(1)* %out
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ret void
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}
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; Make sure the VOP3 form of sub is initially selected. Otherwise pair
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; of opies from/to VCC would be necessary
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; GCN-LABEL: {{^}}sub_select_vop3:
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; SI: v_subrev_i32_e64 v0, s[0:1], s0, v0
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; VI: v_subrev_u32_e64 v0, s[0:1], s0, v0
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; GFX9: v_subrev_u32_e32 v0, s0, v0
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; GCN: ; def vcc
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; GCN: ds_write_b32
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; GCN: ; use vcc
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define amdgpu_ps void @sub_select_vop3(i32 inreg %s, i32 %v) {
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%vcc = call i64 asm sideeffect "; def vcc", "={vcc}"()
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%sub = sub i32 %v, %s
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store i32 %sub, i32 addrspace(3)* undef
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call void asm sideeffect "; use vcc", "{vcc}"(i64 %vcc)
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ret void
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}
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