da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
587 lines
16 KiB
LLVM
587 lines
16 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}uniform_if_scc:
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; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0
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; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
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; GCN: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]]
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; Fall-through to the else
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; GCN: s_mov_b32 [[S_VAL]], 1
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; GCN: [[IF_LABEL]]:
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; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
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; GCN: buffer_store_dword [[V_VAL]]
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define amdgpu_kernel void @uniform_if_scc(i32 %cond, i32 addrspace(1)* %out) {
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entry:
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%cmp0 = icmp eq i32 %cond, 0
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br i1 %cmp0, label %if, label %else
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if:
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br label %done
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else:
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br label %done
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done:
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%value = phi i32 [0, %if], [1, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}uniform_if_vcc:
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; GCN-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
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; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
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; GCN: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
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; Fall-through to the else
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; GCN: s_mov_b32 [[S_VAL]], 1
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; GCN: [[IF_LABEL]]:
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; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
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; GCN: buffer_store_dword [[V_VAL]]
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define amdgpu_kernel void @uniform_if_vcc(float %cond, i32 addrspace(1)* %out) {
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entry:
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%cmp0 = fcmp oeq float %cond, 0.0
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br i1 %cmp0, label %if, label %else
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if:
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br label %done
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else:
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br label %done
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done:
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%value = phi i32 [0, %if], [1, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}uniform_if_swap_br_targets_scc:
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; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
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; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
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; GCN: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]]
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; Fall-through to the else
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; GCN: s_mov_b32 [[S_VAL]], 1
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; GCN: [[IF_LABEL]]:
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; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
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; GCN: buffer_store_dword [[V_VAL]]
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define amdgpu_kernel void @uniform_if_swap_br_targets_scc(i32 %cond, i32 addrspace(1)* %out) {
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entry:
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%cmp0 = icmp eq i32 %cond, 0
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br i1 %cmp0, label %else, label %if
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if:
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br label %done
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else:
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br label %done
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done:
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%value = phi i32 [0, %if], [1, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}uniform_if_swap_br_targets_vcc:
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; GCN-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
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; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
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; GCN: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
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; Fall-through to the else
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; GCN: s_mov_b32 [[S_VAL]], 1
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; GCN: [[IF_LABEL]]:
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; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
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; GCN: buffer_store_dword [[V_VAL]]
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define amdgpu_kernel void @uniform_if_swap_br_targets_vcc(float %cond, i32 addrspace(1)* %out) {
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entry:
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%cmp0 = fcmp oeq float %cond, 0.0
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br i1 %cmp0, label %else, label %if
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if:
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br label %done
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else:
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br label %done
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done:
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%value = phi i32 [0, %if], [1, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}uniform_if_move_valu:
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; GCN: v_add_f32_e32 [[CMP:v[0-9]+]]
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; Using a floating-point value in an integer compare will cause the compare to
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; be selected for the SALU and then later moved to the VALU.
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; GCN: v_cmp_ne_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]]
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; GCN: s_and_b64 vcc, exec, [[COND]]
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; GCN: s_cbranch_vccnz [[ENDIF_LABEL:.L[0-9_A-Za-z]+]]
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; GCN: buffer_store_dword
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; GCN: [[ENDIF_LABEL]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @uniform_if_move_valu(i32 addrspace(1)* %out, float %a) {
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entry:
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%a.0 = fadd float %a, 10.0
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%cond = bitcast float %a.0 to i32
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%cmp = icmp eq i32 %cond, 5
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br i1 %cmp, label %if, label %endif
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if:
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store i32 0, i32 addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}uniform_if_move_valu_commute:
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; GCN: v_add_f32_e32 [[CMP:v[0-9]+]]
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; Using a floating-point value in an integer compare will cause the compare to
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; be selected for the SALU and then later moved to the VALU.
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; GCN: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]]
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; GCN: s_and_b64 vcc, exec, [[COND]]
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; GCN: s_cbranch_vccnz [[ENDIF_LABEL:.L[0-9_A-Za-z]+]]
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; GCN: buffer_store_dword
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; GCN: [[ENDIF_LABEL]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @uniform_if_move_valu_commute(i32 addrspace(1)* %out, float %a) {
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entry:
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%a.0 = fadd float %a, 10.0
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%cond = bitcast float %a.0 to i32
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%cmp = icmp ugt i32 %cond, 5
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br i1 %cmp, label %if, label %endif
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if:
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store i32 0, i32 addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}uniform_if_else_ret:
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_scc0 [[IF_LABEL:.L[0-9_A-Za-z]+]]
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; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
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; GCN: buffer_store_dword [[TWO]]
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; GCN: s_endpgm
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; GCN: {{^}}[[IF_LABEL]]:
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; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
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; GCN: buffer_store_dword [[ONE]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uniform_if_else_ret(i32 addrspace(1)* nocapture %out, i32 %a) {
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entry:
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%cmp = icmp eq i32 %a, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 1, i32 addrspace(1)* %out
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br label %if.end
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if.else: ; preds = %entry
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store i32 2, i32 addrspace(1)* %out
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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; GCN-LABEL: {{^}}uniform_if_else:
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_scc0 [[IF_LABEL:.L[0-9_A-Za-z]+]]
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; GCN: v_mov_b32_e32 [[IMM_REG:v[0-9]+]], 2
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; GCN: s_branch [[ENDIF_LABEL:.L[0-9_A-Za-z]+]]
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; GCN: [[IF_LABEL]]:
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; GCN: v_mov_b32_e32 [[IMM_REG]], 1
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; GCN-NEXT: [[ENDIF_LABEL]]:
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; GCN: buffer_store_dword [[IMM_REG]]
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; GCN: v_mov_b32_e32 [[THREE:v[0-9]+]], 3
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; GCN: buffer_store_dword [[THREE]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uniform_if_else(i32 addrspace(1)* nocapture %out0, i32 addrspace(1)* nocapture %out1, i32 %a) {
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entry:
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%cmp = icmp eq i32 %a, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 1, i32 addrspace(1)* %out0
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br label %if.end
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if.else: ; preds = %entry
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store i32 2, i32 addrspace(1)* %out0
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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store i32 3, i32 addrspace(1)* %out1
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ret void
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}
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; GCN-LABEL: {{^}}icmp_2_users:
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; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1
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; GCN: s_cbranch_scc1 [[LABEL:.L[0-9_A-Za-z]+]]
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; GCN: buffer_store_dword
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; GCN: [[LABEL]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) {
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main_body:
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%0 = icmp sgt i32 %cond, 0
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%1 = sext i1 %0 to i32
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br i1 %0, label %IF, label %ENDIF
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IF:
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store i32 %1, i32 addrspace(1)* %out
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br label %ENDIF
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ENDIF: ; preds = %IF, %main_body
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ret void
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}
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; GCN-LABEL: {{^}}icmp_users_different_blocks:
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; GCN: s_load_dwordx2 s{{\[}}[[COND0:[0-9]+]]:[[COND1:[0-9]+]]{{\]}}
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; GCN: s_cmp_lt_i32 s[[COND0]], 1
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; GCN: s_cbranch_scc1 [[EXIT:.L[0-9_A-Za-z]+]]
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; GCN: s_cmp_gt_i32 s[[COND1]], 0{{$}}
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; GCN: s_cbranch_vccz [[BODY:.L[0-9_A-Za-z]+]]
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; GCN: {{^}}[[EXIT]]:
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; GCN: s_endpgm
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; GCN: {{^}}[[BODY]]:
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; GCN: buffer_store
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; GCN: s_endpgm
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define amdgpu_kernel void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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%cmp0 = icmp sgt i32 %cond0, 0
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%cmp1 = icmp sgt i32 %cond1, 0
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br i1 %cmp0, label %bb2, label %bb9
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bb2: ; preds = %bb
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%tmp2 = sext i1 %cmp1 to i32
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%tmp3 = add i32 %tmp2, %tmp
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br i1 %cmp1, label %bb9, label %bb7
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bb7: ; preds = %bb5
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store i32 %tmp3, i32 addrspace(1)* %out
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br label %bb9
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bb9: ; preds = %bb8, %bb4
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ret void
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}
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; SI-LABEL: {{^}}uniform_loop:
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; SI: {{^}}[[LOOP_LABEL:.L[0-9_A-Za-z]+]]:
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; SI: s_add_i32 [[I:s[0-9]+]], s{{[0-9]+}}, -1
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; SI: s_cmp_lg_u32 [[I]], 0
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; SI: s_cbranch_scc1 [[LOOP_LABEL]]
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; SI: s_endpgm
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define amdgpu_kernel void @uniform_loop(i32 addrspace(1)* %out, i32 %a) {
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entry:
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br label %loop
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loop:
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%i = phi i32 [0, %entry], [%i.i, %loop]
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%i.i = add i32 %i, 1
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%cmp = icmp eq i32 %a, %i.i
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br i1 %cmp, label %done, label %loop
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done:
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ret void
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}
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; Test uniform and divergent.
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; GCN-LABEL: {{^}}uniform_inside_divergent:
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; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
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; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN: s_cmp_lg_u32 {{s[0-9]+}}, 0
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; GCN: s_cbranch_scc0 [[IF_UNIFORM_LABEL:.L[0-9_A-Za-z]+]]
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; GCN: s_endpgm
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; GCN: {{^}}[[IF_UNIFORM_LABEL]]:
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; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
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; GCN: buffer_store_dword [[ONE]]
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define amdgpu_kernel void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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%d_cmp = icmp ult i32 %tid, 16
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br i1 %d_cmp, label %if, label %endif
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if:
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store i32 0, i32 addrspace(1)* %out
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%u_cmp = icmp eq i32 %cond, 0
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br i1 %u_cmp, label %if_uniform, label %endif
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if_uniform:
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store i32 1, i32 addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}divergent_inside_uniform:
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_scc0 [[IF_LABEL:.L[0-9_A-Za-z]+]]
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; GCN: [[ENDIF_LABEL:.L[0-9_A-Za-z]+]]:
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; GCN: [[IF_LABEL]]:
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; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
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; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN: s_cbranch_execz [[ENDIF_LABEL]]
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; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
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; GCN: buffer_store_dword [[ONE]]
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; GCN: s_endpgm
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define amdgpu_kernel void @divergent_inside_uniform(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%u_cmp = icmp eq i32 %cond, 0
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br i1 %u_cmp, label %if, label %endif
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if:
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store i32 0, i32 addrspace(1)* %out
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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%d_cmp = icmp ult i32 %tid, 16
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br i1 %d_cmp, label %if_uniform, label %endif
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if_uniform:
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store i32 1, i32 addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}divergent_if_uniform_if:
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; GCN: v_cmp_eq_u32_e32 vcc, 0, v0
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; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
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; GCN: buffer_store_dword [[ONE]]
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; GCN: s_or_b64 exec, exec, [[MASK]]
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_scc0 [[IF_UNIFORM:.L[0-9_A-Za-z]+]]
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; GCN: s_endpgm
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; GCN: [[IF_UNIFORM]]:
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; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
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; GCN: buffer_store_dword [[TWO]]
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define amdgpu_kernel void @divergent_if_uniform_if(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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%d_cmp = icmp eq i32 %tid, 0
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br i1 %d_cmp, label %if, label %endif
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if:
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store i32 1, i32 addrspace(1)* %out
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br label %endif
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endif:
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%u_cmp = icmp eq i32 %cond, 0
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br i1 %u_cmp, label %if_uniform, label %exit
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if_uniform:
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store i32 2, i32 addrspace(1)* %out
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br label %exit
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exit:
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ret void
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}
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; The condition of the branches in the two blocks are
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; uniform. MachineCSE replaces the 2nd condition with the inverse of
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; the first, leaving an scc use in a different block than it was
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; defed.
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; GCN-LABEL: {{^}}cse_uniform_condition_different_blocks:
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; GCN: s_load_dword [[COND:s[0-9]+]]
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; GCN: s_cmp_lt_i32 [[COND]], 1
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; GCN: s_cbranch_scc1 .LBB[[FNNUM:[0-9]+]]_3
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; GCN: %bb.1:
|
|
; GCN-NOT: cmp
|
|
; GCN: buffer_load_dword
|
|
; GCN: buffer_store_dword
|
|
; GCN: s_cbranch_scc1 .LBB[[FNNUM]]_3
|
|
|
|
; GCN: .LBB[[FNNUM]]_3:
|
|
; GCN: s_endpgm
|
|
define amdgpu_kernel void @cse_uniform_condition_different_blocks(i32 %cond, i32 addrspace(1)* %out) {
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
%tmp1 = icmp sgt i32 %cond, 0
|
|
br i1 %tmp1, label %bb2, label %bb9
|
|
|
|
bb2: ; preds = %bb
|
|
%tmp3 = load volatile i32, i32 addrspace(1)* undef
|
|
store volatile i32 0, i32 addrspace(1)* undef
|
|
%tmp9 = icmp sle i32 %cond, 0
|
|
br i1 %tmp9, label %bb9, label %bb7
|
|
|
|
bb7: ; preds = %bb5
|
|
store i32 %tmp3, i32 addrspace(1)* %out
|
|
br label %bb9
|
|
|
|
bb9: ; preds = %bb8, %bb4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}uniform_if_scc_i64_eq:
|
|
; VI-DAG: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, 0
|
|
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
|
|
; SI-DAG: v_cmp_eq_u64_e64
|
|
; SI: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
|
|
|
|
; VI: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]]
|
|
|
|
; Fall-through to the else
|
|
; GCN: s_mov_b32 [[S_VAL]], 1
|
|
|
|
; GCN: [[IF_LABEL]]:
|
|
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
|
|
; GCN: buffer_store_dword [[V_VAL]]
|
|
define amdgpu_kernel void @uniform_if_scc_i64_eq(i64 %cond, i32 addrspace(1)* %out) {
|
|
entry:
|
|
%cmp0 = icmp eq i64 %cond, 0
|
|
br i1 %cmp0, label %if, label %else
|
|
|
|
if:
|
|
br label %done
|
|
|
|
else:
|
|
br label %done
|
|
|
|
done:
|
|
%value = phi i32 [0, %if], [1, %else]
|
|
store i32 %value, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}uniform_if_scc_i64_ne:
|
|
; VI-DAG: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, 0
|
|
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
|
|
|
|
; SI-DAG: v_cmp_ne_u64_e64
|
|
; SI: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
|
|
|
|
; VI: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]]
|
|
|
|
; Fall-through to the else
|
|
; GCN: s_mov_b32 [[S_VAL]], 1
|
|
|
|
; GCN: [[IF_LABEL]]:
|
|
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
|
|
; GCN: buffer_store_dword [[V_VAL]]
|
|
define amdgpu_kernel void @uniform_if_scc_i64_ne(i64 %cond, i32 addrspace(1)* %out) {
|
|
entry:
|
|
%cmp0 = icmp ne i64 %cond, 0
|
|
br i1 %cmp0, label %if, label %else
|
|
|
|
if:
|
|
br label %done
|
|
|
|
else:
|
|
br label %done
|
|
|
|
done:
|
|
%value = phi i32 [0, %if], [1, %else]
|
|
store i32 %value, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}uniform_if_scc_i64_sgt:
|
|
; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0
|
|
; GCN-DAG: v_cmp_gt_i64_e64
|
|
; GCN: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]]
|
|
|
|
; Fall-through to the else
|
|
; GCN: s_mov_b32 [[S_VAL]], 1
|
|
|
|
; GCN: [[IF_LABEL]]:
|
|
; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]]
|
|
; GCN: buffer_store_dword [[V_VAL]]
|
|
define amdgpu_kernel void @uniform_if_scc_i64_sgt(i64 %cond, i32 addrspace(1)* %out) {
|
|
entry:
|
|
%cmp0 = icmp sgt i64 %cond, 0
|
|
br i1 %cmp0, label %if, label %else
|
|
|
|
if:
|
|
br label %done
|
|
|
|
else:
|
|
br label %done
|
|
|
|
done:
|
|
%value = phi i32 [0, %if], [1, %else]
|
|
store i32 %value, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}move_to_valu_i64_eq:
|
|
; GCN: v_cmp_eq_u64_e32
|
|
define amdgpu_kernel void @move_to_valu_i64_eq(i32 addrspace(1)* %out) {
|
|
%cond = load volatile i64, i64 addrspace(3)* undef
|
|
%cmp0 = icmp eq i64 %cond, 0
|
|
br i1 %cmp0, label %if, label %else
|
|
|
|
if:
|
|
br label %done
|
|
|
|
else:
|
|
br label %done
|
|
|
|
done:
|
|
%value = phi i32 [0, %if], [1, %else]
|
|
store i32 %value, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}move_to_valu_i64_ne:
|
|
; GCN: v_cmp_ne_u64_e32
|
|
define amdgpu_kernel void @move_to_valu_i64_ne(i32 addrspace(1)* %out) {
|
|
%cond = load volatile i64, i64 addrspace(3)* undef
|
|
%cmp0 = icmp ne i64 %cond, 0
|
|
br i1 %cmp0, label %if, label %else
|
|
|
|
if:
|
|
br label %done
|
|
|
|
else:
|
|
br label %done
|
|
|
|
done:
|
|
%value = phi i32 [0, %if], [1, %else]
|
|
store i32 %value, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}move_to_valu_vgpr_operand_phi:
|
|
; GCN: v_add_{{[iu]}}32_e32
|
|
; GCN: ds_write_b32
|
|
define void @move_to_valu_vgpr_operand_phi(i32 addrspace(3)* %out) {
|
|
bb0:
|
|
br label %bb1
|
|
|
|
bb1: ; preds = %bb3, %bb0
|
|
%tmp0 = phi i32 [ 8, %bb0 ], [ %tmp4, %bb3 ]
|
|
%tmp1 = add nsw i32 %tmp0, -1
|
|
%tmp2 = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tmp1
|
|
br i1 undef, label %bb2, label %bb3
|
|
|
|
bb2: ; preds = %bb1
|
|
store volatile i32 1, i32 addrspace(3)* %tmp2, align 4
|
|
br label %bb3
|
|
|
|
bb3: ; preds = %bb2, %bb1
|
|
%tmp4 = add nsw i32 %tmp0, 2
|
|
br label %bb1
|
|
}
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
|
attributes #0 = { nounwind readnone }
|