2caf85ad7a
Currently, LOAD_STACK_GUARD on ARM is only implemented for Mach-O targets, and other targets rely on the generic support which may result in spilling of the stack canary value or address, or may cause it to be kept in a callee save register across function calls, which means they essentially get spilled as well, only by the callee when it wants to free up this register. So let's implement LOAD_STACK GUARD for other targets as well. This ensures that the load of the stack canary is rematerialized fully in the epilogue. This code was split off from D112768: [ARM] implement support for TLS register based stack protector for which it is a prerequisite. Reviewed By: nickdesaulniers Differential Revision: https://reviews.llvm.org/D112811
27 lines
978 B
LLVM
27 lines
978 B
LLVM
; RUN: llc -mtriple=thumbv7-w64-mingw32 < %s -o - | FileCheck --check-prefix=MINGW %s
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declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
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declare dso_local void @other(i8*)
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declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
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define dso_local void @func() sspstrong {
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entry:
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; MINGW-LABEL: func:
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; MINGW: movw [[REG:r[0-9]+]], :lower16:.refptr.__stack_chk_guard
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; MINGW: movt [[REG]], :upper16:.refptr.__stack_chk_guard
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; MINGW: ldr [[REG2:r[0-9]+]], {{\[}}[[REG]]]
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; MINGW: ldr {{r[0-9]+}}, {{\[}}[[REG2]]]
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; MINGW: bl other
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; MINGW: movw [[REG3:r[0-9]+]], :lower16:.refptr.__stack_chk_guard
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; MINGW: movt [[REG3]], :upper16:.refptr.__stack_chk_guard
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; MINGW: ldr [[REG4:r[0-9]+]], {{\[}}[[REG3]]]
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; MINGW: ldr {{r[0-9]+}}, {{\[}}[[REG4]]]
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; MINGW: bl __stack_chk_fail
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%c = alloca i8, align 1
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call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %c)
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call void @other(i8* nonnull %c)
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call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %c)
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ret void
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}
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