51eefa8164
These registers are used as operands for instructions that expect an
integer register, so they should be added to Int32Regs or Int64Regs
register classes. Otherwise the machine verifier emits an error for
the following LIT tests when LLVM_ENABLE_MACHINE_VERIFIER=1
environment variable is set:
*** Bad machine code: Illegal physical register for instruction ***
- function: kernel_func
- basic block: %bb.0 entry (0x55c8903d5438)
- instruction: %3:int64regs = LEA_ADDRi64 $vrframelocal, 0
- operand 1: $vrframelocal
$vrframelocal is not a Int64Regs register.
CodeGen/NVPTX/call-with-alloca-buffer.ll
CodeGen/NVPTX/disable-opt.ll
CodeGen/NVPTX/lower-alloca.ll
CodeGen/NVPTX/lower-args.ll
CodeGen/NVPTX/param-align.ll
CodeGen/NVPTX/reg-types.ll
DebugInfo/NVPTX/dbg-declare-alloca.ll
DebugInfo/NVPTX/dbg-value-const-byref.ll
Differential Revision: https://reviews.llvm.org/D110164
83 lines
3.3 KiB
LLVM
83 lines
3.3 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s --check-prefix=PTX32
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s --check-prefix=PTX64
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; Ensure we access the local stack properly
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; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}};
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; PTX32: cvta.local.u32 %SP, %SPL;
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; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo_param_0];
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; PTX32: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
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; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
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; PTX64: cvta.local.u64 %SP, %SPL;
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; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo_param_0];
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; PTX64: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
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define void @foo(i32 %a) {
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%local = alloca i32, align 4
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store volatile i32 %a, i32* %local
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ret void
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}
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; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}};
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; PTX32: cvta.local.u32 %SP, %SPL;
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; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo2_param_0];
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; PTX32: add.u32 %r[[SP_REG:[0-9]+]], %SPL, 0;
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; PTX32: st.local.u32 [%r[[SP_REG]]], %r{{[0-9]+}};
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; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
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; PTX64: cvta.local.u64 %SP, %SPL;
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; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo2_param_0];
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; PTX64: add.u64 %rd[[SP_REG:[0-9]+]], %SPL, 0;
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; PTX64: st.local.u32 [%rd[[SP_REG]]], %r{{[0-9]+}};
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define void @foo2(i32 %a) {
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%local = alloca i32, align 4
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store i32 %a, i32* %local
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call void @bar(i32* %local)
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ret void
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}
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declare void @bar(i32* %a)
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!nvvm.annotations = !{!0}
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!0 = !{void (i32)* @foo2, !"kernel", i32 1}
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; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}};
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; PTX32-NOT: cvta.local.u32 %SP, %SPL;
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; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo3_param_0];
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; PTX32: add.u32 %r{{[0-9]+}}, %SPL, 0;
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; PTX32: st.local.u32 [%r{{[0-9]+}}], %r{{[0-9]+}};
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; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
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; PTX64-NOT: cvta.local.u64 %SP, %SPL;
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; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo3_param_0];
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; PTX64: add.u64 %rd{{[0-9]+}}, %SPL, 0;
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; PTX64: st.local.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}};
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define void @foo3(i32 %a) {
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%local = alloca [3 x i32], align 4
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%1 = bitcast [3 x i32]* %local to i32*
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%2 = getelementptr inbounds i32, i32* %1, i32 %a
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store i32 %a, i32* %2
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ret void
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}
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; PTX32: cvta.local.u32 %SP, %SPL;
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; PTX32: add.u32 {{%r[0-9]+}}, %SP, 0;
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; PTX32: add.u32 {{%r[0-9]+}}, %SPL, 0;
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; PTX32: add.u32 {{%r[0-9]+}}, %SP, 4;
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; PTX32: add.u32 {{%r[0-9]+}}, %SPL, 4;
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; PTX32: st.local.u32 [{{%r[0-9]+}}], {{%r[0-9]+}}
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; PTX32: st.local.u32 [{{%r[0-9]+}}], {{%r[0-9]+}}
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; PTX64: cvta.local.u64 %SP, %SPL;
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; PTX64: add.u64 {{%rd[0-9]+}}, %SP, 0;
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; PTX64: add.u64 {{%rd[0-9]+}}, %SPL, 0;
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; PTX64: add.u64 {{%rd[0-9]+}}, %SP, 4;
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; PTX64: add.u64 {{%rd[0-9]+}}, %SPL, 4;
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; PTX64: st.local.u32 [{{%rd[0-9]+}}], {{%r[0-9]+}}
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; PTX64: st.local.u32 [{{%rd[0-9]+}}], {{%r[0-9]+}}
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define void @foo4() {
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%A = alloca i32
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%B = alloca i32
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store i32 0, i32* %A
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store i32 0, i32* %B
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call void @bar(i32* %A)
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call void @bar(i32* %B)
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ret void
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}
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