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clang-p2996/llvm/test/CodeGen/VE/Vector
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Simon Moll b2cea573c9 [VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests 
Depends on D115940 for the `Binary_rv_vr_vv` pattern class op isel
fragment used for divisions.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D116035
2021-12-21 09:15:31 +01:00
..
expand_single_elem_build_vec.ll
…
extract_elt.ll
[VE] Extract & insert vector element isel
2021-01-08 11:46:59 +01:00
fastcc_callee.ll
…
fastcc_caller.ll
…
feature_vpu.ll
[VE] Add +vpu attribute
2020-11-04 12:42:00 +01:00
insert_elt.ll
[VE] Expand single-element BUILD_VECTOR to INSERT_VECTOR_ELT
2021-01-08 11:48:01 +01:00
vec_add.ll
[VE] Change the behaviour of truncate
2020-11-30 22:12:45 +09:00
vec_and.ll
[VE] Vector 'and' isel and tests
2020-12-23 13:29:29 +01:00
vec_broadcast.ll
[VE] Change the behaviour of truncate
2020-11-30 22:12:45 +09:00
vp_add.ll
[VP] ISD helper functions [VE] isel for vp_add, vp_and
2021-01-08 14:29:45 +01:00
vp_and.ll
…
vp_ashr.ll
[VE] SHL,SRA,SRL v256i32|64 isel and tests
2021-12-15 11:32:18 +01:00
vp_fadd.ll
[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
2021-12-21 09:15:31 +01:00
vp_fdiv.ll
[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
2021-12-21 09:15:31 +01:00
vp_fmul.ll
[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
2021-12-21 09:15:31 +01:00
vp_fsub.ll
[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
2021-12-21 09:15:31 +01:00
vp_lshr.ll
[VE] SHL,SRA,SRL v256i32|64 isel and tests
2021-12-15 11:32:18 +01:00
vp_mul.ll
…
vp_or.ll
[VE] MUL,SUB,OR,XOR v256i32|64 isel
2021-12-14 13:23:48 +01:00
vp_sdiv.ll
[VE] U|SDIV v256i32|64 isel and tests
2021-12-21 08:51:01 +01:00
vp_shl.ll
[VE] SHL,SRA,SRL v256i32|64 isel and tests
2021-12-15 11:32:18 +01:00
vp_sra.ll
[VE] SHL,SRA,SRL v256i32|64 isel and tests
2021-12-15 11:32:18 +01:00
vp_srem.ll
…
vp_srl.ll
[VE] SHL,SRA,SRL v256i32|64 isel and tests
2021-12-15 11:32:18 +01:00
vp_sub.ll
[VE] MUL,SUB,OR,XOR v256i32|64 isel
2021-12-14 13:23:48 +01:00
vp_udiv.ll
[VE] U|SDIV v256i32|64 isel and tests
2021-12-21 08:51:01 +01:00
vp_urem.ll
…
vp_xor.ll
…