6599961c17
This patch contains following enhancements to SrcRegMap and DstRegMap:
1 In findOnlyInterestingUse not only check if the Reg is two address usage,
but also check after commutation can it be two address usage.
2 If a physical register is clobbered, remove SrcRegMap entries that are
mapped to it.
3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap
entry only when the COPY instruction is coalescable. (The COPY src is
killed)
With these enhancements isProfitableToCommute can do better commute decision,
and finally more register copies are removed.
Differential Revision: https://reviews.llvm.org/D108731
190 lines
5.6 KiB
LLVM
190 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
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define i8 @shl_and(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: shl_and:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: leal (,%rsi,4), %eax
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; CHECK-NEXT: shlb $5, %dil
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; CHECK-NEXT: andb %dil, %al
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%sh0 = shl i8 %x, 3
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%r = and i8 %sh0, %y
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%sh1 = shl i8 %r, 2
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ret i8 %sh1
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}
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define i16 @shl_or(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: shl_or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll $7, %esi
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; CHECK-NEXT: shll $12, %eax
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; CHECK-NEXT: orl %esi, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%sh0 = shl i16 %x, 5
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%r = or i16 %y, %sh0
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%sh1 = shl i16 %r, 7
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ret i16 %sh1
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}
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define i32 @shl_xor(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: shl_xor:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll $7, %esi
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; CHECK-NEXT: shll $12, %eax
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; CHECK-NEXT: xorl %esi, %eax
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; CHECK-NEXT: retq
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%sh0 = shl i32 %x, 5
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%r = xor i32 %sh0, %y
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%sh1 = shl i32 %r, 7
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ret i32 %sh1
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}
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define i64 @lshr_and(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: lshr_and:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: shrq $7, %rsi
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; CHECK-NEXT: shrq $12, %rax
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; CHECK-NEXT: andq %rsi, %rax
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; CHECK-NEXT: retq
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%sh0 = lshr i64 %x, 5
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%r = and i64 %y, %sh0
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%sh1 = lshr i64 %r, 7
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ret i64 %sh1
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}
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define <4 x i32> @lshr_or(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: lshr_or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrld $7, %xmm1
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; CHECK-NEXT: psrld $12, %xmm0
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%sh0 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
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%r = or <4 x i32> %sh0, %y
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%sh1 = lshr <4 x i32> %r, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %sh1
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}
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define <8 x i16> @lshr_xor(<8 x i16> %x, <8 x i16> %y) nounwind {
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; CHECK-LABEL: lshr_xor:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrlw $7, %xmm1
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; CHECK-NEXT: psrlw $12, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm0
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; CHECK-NEXT: retq
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%sh0 = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%r = xor <8 x i16> %y, %sh0
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%sh1 = lshr <8 x i16> %r, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %sh1
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}
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define <16 x i8> @ashr_and(<16 x i8> %x, <16 x i8> %y) nounwind {
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; CHECK-LABEL: ashr_and:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrlw $2, %xmm1
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; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
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; CHECK-NEXT: pxor %xmm2, %xmm1
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; CHECK-NEXT: psubb %xmm2, %xmm1
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; CHECK-NEXT: psrlw $5, %xmm0
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; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
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; CHECK-NEXT: pxor %xmm2, %xmm0
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; CHECK-NEXT: psubb %xmm2, %xmm0
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; CHECK-NEXT: pand %xmm1, %xmm0
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; CHECK-NEXT: retq
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%sh0 = ashr <16 x i8> %x, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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%r = and <16 x i8> %y, %sh0
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%sh1 = ashr <16 x i8> %r, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
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ret <16 x i8> %sh1
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}
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define <2 x i64> @ashr_or(<2 x i64> %x, <2 x i64> %y) nounwind {
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; CHECK-LABEL: ashr_or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdqa %xmm1, %xmm2
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; CHECK-NEXT: psrad $7, %xmm2
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; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
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; CHECK-NEXT: psrlq $7, %xmm1
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
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; CHECK-NEXT: movdqa %xmm0, %xmm2
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; CHECK-NEXT: psrad $12, %xmm2
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; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
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; CHECK-NEXT: psrlq $12, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%sh0 = ashr <2 x i64> %x, <i64 5, i64 5>
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%r = or <2 x i64> %sh0, %y
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%sh1 = ashr <2 x i64> %r, <i64 7, i64 7>
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ret <2 x i64> %sh1
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}
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define i32 @ashr_xor(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ashr_xor:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarl $7, %esi
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; CHECK-NEXT: sarl $12, %eax
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; CHECK-NEXT: xorl %esi, %eax
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; CHECK-NEXT: retq
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%sh0 = ashr i32 %x, 5
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%r = xor i32 %y, %sh0
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%sh1 = ashr i32 %r, 7
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ret i32 %sh1
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}
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define i32 @shr_mismatch_xor(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: shr_mismatch_xor:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarl $5, %eax
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; CHECK-NEXT: xorl %esi, %eax
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; CHECK-NEXT: shrl $7, %eax
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; CHECK-NEXT: retq
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%sh0 = ashr i32 %x, 5
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%r = xor i32 %y, %sh0
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%sh1 = lshr i32 %r, 7
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ret i32 %sh1
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}
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define i32 @ashr_overshift_xor(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ashr_overshift_xor:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarl $15, %eax
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; CHECK-NEXT: xorl %esi, %eax
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; CHECK-NEXT: sarl $17, %eax
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; CHECK-NEXT: retq
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%sh0 = ashr i32 %x, 15
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%r = xor i32 %y, %sh0
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%sh1 = ashr i32 %r, 17
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ret i32 %sh1
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}
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define i32 @lshr_or_extra_use(i32 %x, i32 %y, i32* %p) nounwind {
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; CHECK-LABEL: lshr_or_extra_use:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: orl %esi, %eax
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; CHECK-NEXT: movl %eax, (%rdx)
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; CHECK-NEXT: shrl $7, %eax
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; CHECK-NEXT: retq
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%sh0 = lshr i32 %x, 5
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%r = or i32 %sh0, %y
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store i32 %r, i32* %p
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%sh1 = lshr i32 %r, 7
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ret i32 %sh1
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}
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