40ddde5d1f
Tablegen currently expects targets to have at least one pressure set for every broader register category. AMDGPU's VGPR or AGPR, for instance, seemed to work correctly without any pset, though we have forced one for each type to avoid the assertion in computeRegUnitSets. However, psets can not be entirely empty. At least one set is mandatory for every target. This patch bypasses the assertion for the classes when GeneratePressureSet is zero while ensuring the RegUnitSets are not empty. Reviewed By: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D110305
68 lines
2.0 KiB
TableGen
68 lines
2.0 KiB
TableGen
// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
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// Test to check the bare minimum pressure sets.
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// At least one register pressure set is required for the target.
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// Allowed the pset only for D_32 regclass and ignored it for all
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// other classes including the tuples.
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include "llvm/Target/Target.td"
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"MyTarget", types, size, registers> {
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let Size = size;
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}
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def sub0 : SubRegIndex<32>;
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def sub1 : SubRegIndex<32, 32>;
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let Namespace = "MyTarget" in {
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def D : Register<"d">;
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foreach Index = 0-7 in {
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def S#Index : Register <"s"#Index>;
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}
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}
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// Should generate psets for D_32
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def D_32 : MyClass<32, [i32], (add D)>;
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let GeneratePressureSet = 0 in {
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def S_32 : MyClass<32, [i32], (sequence "S%u", 0, 7)>;
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def SD_32 : MyClass<32, [i32], (add S_32, D_32)>;
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}
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def S_64 : RegisterTuples<[sub0, sub1],
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[(decimate (shl S_32, 0), 1),
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(decimate (shl S_32, 1), 1)
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]>;
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def SReg_64 : MyClass<64, [i64], (add S_64)> {
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let GeneratePressureSet = 0;
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}
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def MyTarget : Target;
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// CHECK-LABEL: // Register pressure sets enum.
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// CHECK-NEXT: namespace MyTarget {
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// CHECK-NEXT: enum RegisterPressureSets {
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// CHECK-NEXT: D_32 = 0,
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// CHECK-NEXT: };
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// NAMESPACE-NEXT: } // end namespace TestNamespace
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// CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
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// CHECK-NEXT: static const char *const PressureNameTable[] = {
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// CHECK-NEXT: "D_32",
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// CHECK-NEXT: };
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// CHECK-NEXT: return PressureNameTable[Idx];
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// CHECK-NEXT: }
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// CHECK: unsigned MyTargetGenRegisterInfo::
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// CHECK-NEXT: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
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// CHECK-NEXT: static const uint8_t PressureLimitTable[] = {
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// CHECK-NEXT: {{[0-9]+}}, // 0: D_32
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// CHECK-NEXT: };
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// CHECK-NEXT: return PressureLimitTable[Idx];
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// CHECK-NEXT:}
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// CHECK: static const int RCSetsTable[] = {
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// CHECK-NEXT: /* 0 */ 0, -1,
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// CHECK-NEXT: };
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