1a60ae02c6
~(iN X s>> (N-1)) & Y --> (X s< 0) ? 0 : Y
https://alive2.llvm.org/ce/z/JKlQ9x
This is similar to D111410 / 727e642e97 ,
but it includes a 'not' of the signbit and so it
saves an instruction in the basic pattern.
DAGCombiner or target-specific folds can expand
this back into bit-hacks.
The diffs in the logical-select tests are not true
regressions - running early-cse and another round
of instcombine is expected in a normal opt pipeline,
and that reduces back to a minimal form as shown
in the duplicated PhaseOrdering test.
I have no understanding of the SystemZ diffs, so
I made the minimal edits suggested by FileCheck to
make that test pass again. That whole test file is
wrong though. It is running the entire optimizer (-O2)
to check IR, and then topping that by even running
codegen and checking asm. It needs to be split up.
Fixes #52631
70 lines
3.0 KiB
LLVM
70 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define <4 x i32> @vec_select(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @vec_select(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
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; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
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; CHECK-NEXT: [[T2:%.*]] = select <4 x i1> [[ISNEG]], <4 x i32> zeroinitializer, <4 x i32> [[A]]
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; CHECK-NEXT: [[ISNEG1:%.*]] = icmp slt <4 x i32> [[B]], zeroinitializer
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; CHECK-NEXT: [[T3:%.*]] = select <4 x i1> [[ISNEG1]], <4 x i32> [[SUB]], <4 x i32> zeroinitializer
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; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
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; CHECK-NEXT: ret <4 x i32> [[COND]]
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;
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%cmp = icmp slt <4 x i32> %b, zeroinitializer
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%sub = sub nsw <4 x i32> zeroinitializer, %a
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%t0 = icmp slt <4 x i32> %sext, zeroinitializer
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%sext3 = sext <4 x i1> %t0 to <4 x i32>
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%t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
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%t2 = and <4 x i32> %a, %t1
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%t3 = and <4 x i32> %sext3, %sub
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%cond = or <4 x i32> %t2, %t3
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ret <4 x i32> %cond
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}
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define <4 x i32> @vec_select_alternate_sign_bit_test(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @vec_select_alternate_sign_bit_test(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
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; CHECK-NEXT: [[ISNEG1:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
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; CHECK-NEXT: [[T2:%.*]] = select <4 x i1> [[ISNEG1]], <4 x i32> [[A]], <4 x i32> zeroinitializer
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; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt <4 x i32> [[B]], zeroinitializer
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; CHECK-NEXT: [[T3:%.*]] = select <4 x i1> [[ISNEG]], <4 x i32> zeroinitializer, <4 x i32> [[SUB]]
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; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
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; CHECK-NEXT: ret <4 x i32> [[COND]]
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;
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%cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%sub = sub nsw <4 x i32> zeroinitializer, %a
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%t0 = icmp slt <4 x i32> %sext, zeroinitializer
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%sext3 = sext <4 x i1> %t0 to <4 x i32>
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%t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
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%t2 = and <4 x i32> %a, %t1
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%t3 = and <4 x i32> %sext3, %sub
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%cond = or <4 x i32> %t2, %t3
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ret <4 x i32> %cond
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}
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define <2 x i32> @is_negative_undef_elt(<2 x i32> %a) {
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; CHECK-LABEL: @is_negative_undef_elt(
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; CHECK-NEXT: [[A_LOBIT:%.*]] = ashr <2 x i32> [[A:%.*]], <i32 31, i32 31>
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; CHECK-NEXT: ret <2 x i32> [[A_LOBIT]]
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;
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%cmp = icmp slt <2 x i32> %a, <i32 0, i32 undef>
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%sext = sext <2 x i1> %cmp to <2 x i32>
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ret <2 x i32> %sext
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}
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define <2 x i32> @is_positive_undef_elt(<2 x i32> %a) {
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; CHECK-LABEL: @is_positive_undef_elt(
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; CHECK-NEXT: [[A_LOBIT:%.*]] = ashr <2 x i32> [[A:%.*]], <i32 31, i32 31>
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; CHECK-NEXT: [[A_LOBIT_NOT:%.*]] = xor <2 x i32> [[A_LOBIT]], <i32 -1, i32 -1>
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; CHECK-NEXT: ret <2 x i32> [[A_LOBIT_NOT]]
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;
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%cmp = icmp sgt <2 x i32> %a, <i32 undef, i32 -1>
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%sext = sext <2 x i1> %cmp to <2 x i32>
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ret <2 x i32> %sext
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}
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