65c4d6191f
At the moment, the primary induction variable for the vector loop is
created as part of the skeleton creation. This is tied to creating the
vector loop latch outside of VPlan. This prevents from modeling the
*whole* vector loop in VPlan, which in turn is required to model
preheader and exit blocks in VPlan as well.
This patch introduces a new recipe VPCanonicalIVPHIRecipe to represent the
primary IV in VPlan and CanonicalIVIncrement{NUW} opcodes for
VPInstruction to model the increment.
This allows us to partly retire createInductionVariable. At the moment,
a bit of patching up is done after executing all blocks in the plan.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D113223
64 lines
2.3 KiB
LLVM
64 lines
2.3 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -instcombine -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 -enable-new-pm=0 | FileCheck %s
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; RUN: opt < %s -passes=loop-vectorize,instcombine -force-vector-width=4 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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; CHECK-LABEL: more_than_one_use
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;
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; PR30627. Check that a compare instruction with more than one use is not
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; recognized as uniform and is vectorized.
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;
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; CHECK-NOT: Found uniform instruction: %cond = icmp slt i64 %i.next, %n
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; CHECK: vector.body
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; CHECK: %[[I:.+]] = add nuw nsw <4 x i64> %vec.ind, <i64 1, i64 1, i64 1, i64 1>
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; CHECK: icmp slt <4 x i64> %[[I]], %broadcast.splat
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; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
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;
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define i32 @more_than_one_use(i32* %a, i64 %n) {
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
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%r = phi i32 [ %tmp3, %for.body ], [ 0, %entry ]
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%i.next = add nuw nsw i64 %i, 1
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%cond = icmp slt i64 %i.next, %n
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%tmp0 = select i1 %cond, i64 %i.next, i64 0
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%tmp1 = getelementptr inbounds i32, i32* %a, i64 %tmp0
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%tmp2 = load i32, i32* %tmp1, align 8
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%tmp3 = add i32 %r, %tmp2
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br i1 %cond, label %for.body, label %for.end
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for.end:
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%tmp4 = phi i32 [ %tmp3, %for.body ]
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ret i32 %tmp4
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}
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; Check for crash exposed by D76992.
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; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: loop:
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; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
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; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next
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; CHECK-NEXT: WIDEN ir<%cond0> = icmp ir<%iv>, ir<13>
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; CHECK-NEXT: WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>
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; CHECK-NEXT: EMIT vp<{{.+}}> = VF * UF + vp<[[CAN_IV]]>
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; CHECK-NEXT: No successor
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; CHECK-NEXT: }
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define void @test() {
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%cond0 = icmp ult i64 %iv, 13
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%s = select i1 %cond0, i32 10, i32 20
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond = icmp eq i64 %iv.next, 14
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br i1 %exitcond, label %exit, label %loop
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exit: ; preds = %loop
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ret void
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}
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