4615cc38f3
This patch adds support for getting even-odd general purpose register pairs into and out of inline assembly using the `R` constraint as proposed in riscv-non-isa/riscv-c-api-doc#92 There are a few different pieces to this patch, each of which need their own explanation. - Renames the Register Class used for f64 values on rv32i_zdinx from `GPRPair*` to `GPRF64Pair*`. These register classes are kept broadly unmodified, as their primary value type is used for type inference over selection patterns. This rename affects quite a lot of files. - Adds new `GPRPair*` register classes which will be used for `R` constraints and for instructions that need an even-odd GPR pair. This new type is used for `amocas.d.*`(rv32) and `amocas.q.*`(rv64) in Zacas, instead of the `GPRF64Pair` class being used before. - Marks the new `GPRPair` class legal as for holding a `MVT::Untyped`. Two new RISCVISD node types are added for creating and destructing a pair - `BuildGPRPair` and `SplitGPRPair`, and are introduced when bitcasting to/from the pair type and `untyped`. - Adds functionality to `splitValueIntoRegisterParts` and `joinRegisterPartsIntoValue` to handle changing `i<2*xlen>` MVTs into `untyped` pairs. - Adds an override for `getNumRegisters` to ensure that `i<2*xlen>` values, when going to/from inline assembly, only allocate one (pair) register (they would otherwise allocate two). This is due to a bug in SelectionDAGBuilder.cpp which other backends also work around. - Ensures that Clang understands that `R` is a valid inline assembly constraint. - This also allows `R` to be used for `f64` types on `rv32_zdinx` architectures, where doubles are stored in a GPR pair.
112 lines
3.8 KiB
C
112 lines
3.8 KiB
C
// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// Test RISC-V specific inline assembly constraints and modifiers.
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long test_r(long x) {
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// CHECK-LABEL: define{{.*}} {{i64|i32}} @test_r(
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// CHECK: call {{i64|i32}} asm sideeffect "", "=r,r"({{i64|i32}} %{{.*}})
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long ret;
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asm volatile ("" : "=r"(ret) : "r"(x));
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// CHECK: call {{i64|i32}} asm sideeffect "", "=r,r"({{i64|i32}} %{{.*}})
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asm volatile ("" : "=r"(ret) : "r"(x));
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return ret;
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}
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long test_cr(long x) {
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// CHECK-LABEL: define{{.*}} {{i64|i32}} @test_cr(
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// CHECK: call {{i64|i32}} asm sideeffect "", "=^cr,^cr"({{i64|i32}} %{{.*}})
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long ret;
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asm volatile ("" : "=cr"(ret) : "cr"(x));
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return ret;
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}
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float cf;
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double cd;
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void test_cf(float f, double d) {
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// CHECK-LABEL: define{{.*}} void @test_cf(
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// CHECK: call float asm sideeffect "", "=^cf,^cf"(float %{{.*}})
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asm volatile("" : "=cf"(cf) : "cf"(f));
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// CHECK: call double asm sideeffect "", "=^cf,^cf"(double %{{.*}})
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asm volatile("" : "=cf"(cd) : "cf"(d));
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}
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#if __riscv_xlen == 32
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typedef long long double_xlen_t;
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#elif __riscv_xlen == 64
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typedef __int128_t double_xlen_t;
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#endif
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double_xlen_t test_R_wide_scalar(double_xlen_t p) {
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// CHECK-LABEL: define{{.*}} {{i128|i64}} @test_R_wide_scalar(
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// CHECK: call {{i128|i64}} asm sideeffect "", "=R,R"({{i128|i64}} %{{.*}})
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double_xlen_t ret;
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asm volatile("" : "=R"(ret) : "R"(p));
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return ret;
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}
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void test_I(void) {
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// CHECK-LABEL: define{{.*}} void @test_I()
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// CHECK: call void asm sideeffect "", "I"(i32 2047)
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asm volatile ("" :: "I"(2047));
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// CHECK: call void asm sideeffect "", "I"(i32 -2048)
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asm volatile ("" :: "I"(-2048));
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}
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void test_J(void) {
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// CHECK-LABEL: define{{.*}} void @test_J()
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// CHECK: call void asm sideeffect "", "J"(i32 0)
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asm volatile ("" :: "J"(0));
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}
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void test_K(void) {
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// CHECK-LABEL: define{{.*}} void @test_K()
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// CHECK: call void asm sideeffect "", "K"(i32 31)
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asm volatile ("" :: "K"(31));
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// CHECK: call void asm sideeffect "", "K"(i32 0)
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asm volatile ("" :: "K"(0));
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}
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float f;
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double d;
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void test_f(void) {
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// CHECK-LABEL: define{{.*}} void @test_f()
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// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, ptr @f
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// CHECK: call void asm sideeffect "", "f"(float [[FLT_ARG]])
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asm volatile ("" :: "f"(f));
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// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, ptr @d
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// CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
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asm volatile ("" :: "f"(d));
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}
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void test_A(int *p) {
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// CHECK-LABEL: define{{.*}} void @test_A(ptr noundef %p)
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// CHECK: call void asm sideeffect "", "*A"(ptr elementtype(i32) %p)
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asm volatile("" :: "A"(*p));
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}
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extern int var, arr[2][2];
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struct Pair { int a, b; } pair;
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// CHECK-LABEL: test_s(
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// CHECK: call void asm sideeffect "// $0 $1 $2", "s,s,s"(ptr nonnull @var, ptr nonnull getelementptr inbounds (i8, ptr @arr, {{.*}}), ptr nonnull @test_s)
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// CHECK: call void asm sideeffect "// $0", "s"(ptr nonnull getelementptr inbounds nuw (i8, ptr @pair, {{.*}}))
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// CHECK: call void asm sideeffect "// $0 $1 $2", "S,S,S"(ptr nonnull @var, ptr nonnull getelementptr inbounds (i8, ptr @arr, {{.*}}), ptr nonnull @test_s)
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void test_s(void) {
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asm("// %0 %1 %2" :: "s"(&var), "s"(&arr[1][1]), "s"(test_s));
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asm("// %0" :: "s"(&pair.b));
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asm("// %0 %1 %2" :: "S"(&var), "S"(&arr[1][1]), "S"(test_s));
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}
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// CHECK-LABEL: test_modifiers(
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// CHECK: call void asm sideeffect "// ${0:i} ${1:i}", "r,r"({{i32|i64}} %val, i32 37)
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// CHECK: call void asm sideeffect "// ${0:z} ${1:z}", "i,i"(i32 0, i32 1)
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// CHECK: call void asm sideeffect "// ${0:N}", "r"({{i32|i64}} %val)
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void test_modifiers(long val) {
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asm volatile("// %i0 %i1" :: "r"(val), "r"(37));
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asm volatile("// %z0 %z1" :: "i"(0), "i"(1));
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asm volatile("// %N0" :: "r"(val));
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}
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