91aad9bfb2
The scalar __mfp8 type has the wrong name and mangle name in AArch64SVEACLETypes.def According to the ACLE[1] the name should be __mfp8 This patch fixes this problem by replacing the Name __MFloat8_t by __mfp8 and the Mangle Name __MFloat8_t by u6__mfp8 And we revert the incorrect typedef in NeonEmitter. [1]https://github.com/ARM-software/acle
86 lines
4.1 KiB
C
86 lines
4.1 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// RUN: %clang_cc1 -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-C
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// RUN: %clang_cc1 -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -o - -x c++ %s | FileCheck %s --check-prefixes=CHECK,CHECK-CXX
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// REQUIRES: aarch64-registered-target
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#include <arm_neon.h>
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// CHECK-C-LABEL: define dso_local <16 x i8> @test_ret_mfloat8x16_t(
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// CHECK-C-SAME: <16 x i8> [[V:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-C-NEXT: [[ENTRY:.*:]]
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// CHECK-C-NEXT: [[V_ADDR:%.*]] = alloca <16 x i8>, align 16
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// CHECK-C-NEXT: store <16 x i8> [[V]], ptr [[V_ADDR]], align 16
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// CHECK-C-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[V_ADDR]], align 16
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// CHECK-C-NEXT: ret <16 x i8> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <16 x i8> @_Z21test_ret_mfloat8x16_tu14__MFloat8x16_t(
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// CHECK-CXX-SAME: <16 x i8> [[V:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: [[V_ADDR:%.*]] = alloca <16 x i8>, align 16
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// CHECK-CXX-NEXT: store <16 x i8> [[V]], ptr [[V_ADDR]], align 16
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[V_ADDR]], align 16
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// CHECK-CXX-NEXT: ret <16 x i8> [[TMP0]]
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//
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mfloat8x16_t test_ret_mfloat8x16_t(mfloat8x16_t v) {
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return v;
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}
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// CHECK-C-LABEL: define dso_local <8 x i8> @test_ret_mfloat8x8_t(
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// CHECK-C-SAME: <8 x i8> [[V:%.*]]) #[[ATTR0]] {
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// CHECK-C-NEXT: [[ENTRY:.*:]]
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// CHECK-C-NEXT: [[V_ADDR:%.*]] = alloca <8 x i8>, align 8
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// CHECK-C-NEXT: store <8 x i8> [[V]], ptr [[V_ADDR]], align 8
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// CHECK-C-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[V_ADDR]], align 8
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// CHECK-C-NEXT: ret <8 x i8> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <8 x i8> @_Z20test_ret_mfloat8x8_tu13__MFloat8x8_t(
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// CHECK-CXX-SAME: <8 x i8> [[V:%.*]]) #[[ATTR0]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: [[V_ADDR:%.*]] = alloca <8 x i8>, align 8
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// CHECK-CXX-NEXT: store <8 x i8> [[V]], ptr [[V_ADDR]], align 8
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[V_ADDR]], align 8
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// CHECK-CXX-NEXT: ret <8 x i8> [[TMP0]]
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//
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mfloat8x8_t test_ret_mfloat8x8_t(mfloat8x8_t v) {
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return v;
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}
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// CHECK-C-LABEL: define dso_local <1 x i8> @func1n(
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// CHECK-C-SAME: <1 x i8> [[MFP8:%.*]]) #[[ATTR0]] {
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// CHECK-C-NEXT: [[ENTRY:.*:]]
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// CHECK-C-NEXT: [[MFP8_ADDR:%.*]] = alloca <1 x i8>, align 1
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// CHECK-C-NEXT: [[F1N:%.*]] = alloca [10 x <1 x i8>], align 1
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// CHECK-C-NEXT: store <1 x i8> [[MFP8]], ptr [[MFP8_ADDR]], align 1
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// CHECK-C-NEXT: [[TMP0:%.*]] = load <1 x i8>, ptr [[MFP8_ADDR]], align 1
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// CHECK-C-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x <1 x i8>], ptr [[F1N]], i64 0, i64 2
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// CHECK-C-NEXT: store <1 x i8> [[TMP0]], ptr [[ARRAYIDX]], align 1
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// CHECK-C-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x <1 x i8>], ptr [[F1N]], i64 0, i64 2
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// CHECK-C-NEXT: [[TMP1:%.*]] = load <1 x i8>, ptr [[ARRAYIDX1]], align 1
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// CHECK-C-NEXT: ret <1 x i8> [[TMP1]]
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//
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// CHECK-CXX-LABEL: define dso_local <1 x i8> @_Z6func1nu6__mfp8(
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// CHECK-CXX-SAME: <1 x i8> [[MFP8:%.*]]) #[[ATTR0]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: [[MFP8_ADDR:%.*]] = alloca <1 x i8>, align 1
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// CHECK-CXX-NEXT: [[F1N:%.*]] = alloca [10 x <1 x i8>], align 1
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// CHECK-CXX-NEXT: store <1 x i8> [[MFP8]], ptr [[MFP8_ADDR]], align 1
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = load <1 x i8>, ptr [[MFP8_ADDR]], align 1
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// CHECK-CXX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x <1 x i8>], ptr [[F1N]], i64 0, i64 2
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// CHECK-CXX-NEXT: store <1 x i8> [[TMP0]], ptr [[ARRAYIDX]], align 1
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// CHECK-CXX-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x <1 x i8>], ptr [[F1N]], i64 0, i64 2
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// CHECK-CXX-NEXT: [[TMP1:%.*]] = load <1 x i8>, ptr [[ARRAYIDX1]], align 1
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// CHECK-CXX-NEXT: ret <1 x i8> [[TMP1]]
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//
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__mfp8 func1n(__mfp8 mfp8) {
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__mfp8 f1n[10];
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f1n[2] = mfp8;
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return f1n[2];
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}
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//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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// CHECK: {{.*}}
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