9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
104 lines
2.8 KiB
LLVM
104 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; GCN-LABEL: {{^}}scalar_andn2_i32_one_use
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; GCN: s_andn2_b32
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define amdgpu_kernel void @scalar_andn2_i32_one_use(
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ptr addrspace(1) %r0, i32 %a, i32 %b) {
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entry:
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%nb = xor i32 %b, -1
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%r0.val = and i32 %a, %nb
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store i32 %r0.val, ptr addrspace(1) %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_andn2_i64_one_use
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; GCN: s_andn2_b64
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define amdgpu_kernel void @scalar_andn2_i64_one_use(
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ptr addrspace(1) %r0, i64 %a, i64 %b) {
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entry:
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%nb = xor i64 %b, -1
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%r0.val = and i64 %a, %nb
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store i64 %r0.val, ptr addrspace(1) %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_orn2_i32_one_use
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; GCN: s_orn2_b32
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define amdgpu_kernel void @scalar_orn2_i32_one_use(
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ptr addrspace(1) %r0, i32 %a, i32 %b) {
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entry:
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%nb = xor i32 %b, -1
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%r0.val = or i32 %a, %nb
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store i32 %r0.val, ptr addrspace(1) %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_orn2_i64_one_use
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; GCN: s_orn2_b64
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define amdgpu_kernel void @scalar_orn2_i64_one_use(
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ptr addrspace(1) %r0, i64 %a, i64 %b) {
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entry:
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%nb = xor i64 %b, -1
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%r0.val = or i64 %a, %nb
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store i64 %r0.val, ptr addrspace(1) %r0
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ret void
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}
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; GCN-LABEL: {{^}}vector_andn2_i32_s_v_one_use
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; GCN: v_not_b32
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; GCN: v_and_b32
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define amdgpu_kernel void @vector_andn2_i32_s_v_one_use(
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ptr addrspace(1) %r0, i32 %s) {
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entry:
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%not = xor i32 %v, -1
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%r0.val = and i32 %s, %not
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store i32 %r0.val, ptr addrspace(1) %r0
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ret void
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}
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; GCN-LABEL: {{^}}vector_andn2_i32_v_s_one_use
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; GCN: s_not_b32
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; GCN: v_and_b32
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define amdgpu_kernel void @vector_andn2_i32_v_s_one_use(
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ptr addrspace(1) %r0, i32 %s) {
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entry:
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%not = xor i32 %s, -1
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%r0.val = and i32 %v, %not
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store i32 %r0.val, ptr addrspace(1) %r0
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ret void
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}
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; GCN-LABEL: {{^}}vector_orn2_i32_s_v_one_use
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; GCN: v_not_b32
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; GCN: v_or_b32
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define amdgpu_kernel void @vector_orn2_i32_s_v_one_use(
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ptr addrspace(1) %r0, i32 %s) {
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entry:
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%not = xor i32 %v, -1
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%r0.val = or i32 %s, %not
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store i32 %r0.val, ptr addrspace(1) %r0
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ret void
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}
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; GCN-LABEL: {{^}}vector_orn2_i32_v_s_one_use
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; GCN: s_not_b32
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; GCN: v_or_b32
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define amdgpu_kernel void @vector_orn2_i32_v_s_one_use(
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ptr addrspace(1) %r0, i32 %s) {
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entry:
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%not = xor i32 %s, -1
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%r0.val = or i32 %v, %not
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store i32 %r0.val, ptr addrspace(1) %r0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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