9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
69 lines
3.4 KiB
LLVM
69 lines
3.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx902 -verify-machineinstrs -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}name:{{[ ]*}}vector_clause
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; GCN: S_LOAD_DWORDX4
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; GCN: GLOBAL_LOAD_DWORDX4_SADDR
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; GCN: GLOBAL_LOAD_DWORDX4_SADDR
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; GCN: GLOBAL_LOAD_DWORDX4_SADDR
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; GCN: GLOBAL_LOAD_DWORDX4_SADDR
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; GCN-NEXT: KILL
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define amdgpu_kernel void @vector_clause(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture %arg1) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = zext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp2
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%tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 16
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%tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp2
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%tmp6 = add nuw nsw i64 %tmp2, 1
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%tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp6
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%tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 16
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%tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp6
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%tmp10 = add nuw nsw i64 %tmp2, 2
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%tmp11 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp10
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%tmp12 = load <4 x i32>, ptr addrspace(1) %tmp11, align 16
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%tmp13 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp10
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%tmp14 = add nuw nsw i64 %tmp2, 3
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%tmp15 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp14
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%tmp16 = load <4 x i32>, ptr addrspace(1) %tmp15, align 16
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%tmp17 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp14
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store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 16
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store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 16
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store <4 x i32> %tmp12, ptr addrspace(1) %tmp13, align 16
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store <4 x i32> %tmp16, ptr addrspace(1) %tmp17, align 16
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ret void
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}
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; GCN-LABEL: {{^}}name:{{[ ]*}}no_vector_clause
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; GCN-NOT: BUNDLE
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; GCN-NOT: KILL
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define amdgpu_kernel void @no_vector_clause(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture %arg1) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = zext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp2
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%tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 16
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%tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp2
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%tmp6 = add nuw nsw i64 %tmp2, 1
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%tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp6
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%tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 16
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%tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp6
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%tmp10 = add nuw nsw i64 %tmp2, 2
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%tmp11 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp10
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%tmp12 = load <4 x i32>, ptr addrspace(1) %tmp11, align 16
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%tmp13 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp10
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%tmp14 = add nuw nsw i64 %tmp2, 3
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%tmp15 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp14
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%tmp16 = load <4 x i32>, ptr addrspace(1) %tmp15, align 16
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%tmp17 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp14
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store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 16
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store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 16
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store <4 x i32> %tmp12, ptr addrspace(1) %tmp13, align 16
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store <4 x i32> %tmp16, ptr addrspace(1) %tmp17, align 16
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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attributes #0 = { "amdgpu-max-memory-clause"="1" }
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