52e5683ddd
ARM uses complex encoding of immediate values using small number of bits. As a result, some values cannot be represented as immediate operands, they need to be synthesized in a register. This change implements legalization of such constants with loading values from constant pool. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
26 lines
918 B
YAML
26 lines
918 B
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: get_const
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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constants:
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- id: 0
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value: i32 287454020
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alignment: 4
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isTargetSpecific: false
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body: |
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bb.1.entry:
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; CHECK-LABEL: name: get_const
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; CHECK: [[LDRcp:%[0-9]+]]:gpr = LDRcp %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
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; CHECK-NEXT: $r0 = COPY [[LDRcp]]
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; CHECK-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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%1:gprb(p0) = G_CONSTANT_POOL %const.0
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%0:gprb(s32) = G_LOAD %1(p0) :: (load (s32) from constant-pool)
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$r0 = COPY %0(s32)
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MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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...
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