Shilei Tian 6548b6354d Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)" ...

This reverts commit ca33649abe.

2024-11-08 20:21:16 -05:00

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custom-pseudo-source-values.ll

[AMDGPU] Use resource base for buffer instruction MachineMemOperands

2023-06-05 17:06:57 +00:00

dead-flag-on-use-operand-parse-error.mir

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empty-custom-regmask.mir

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expected-target-index-name.mir

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intrinsics.mir

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invalid-frame-index2.mir

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invalid-frame-index-invalid-fixed-stack.mir

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invalid-frame-index-invalid-stack.mir

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invalid-frame-index-no-stack.mir

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invalid-frame-index.mir

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invalid-target-index-operand.mir

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killed-flag-on-def-parse-error.mir

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lit.local.cfg

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llc-target-cpu-attr-from-cmdline-ir.mir

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llc-target-cpu-attr-from-cmdline.mir

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long-branch-reg-all-sgpr-used.ll

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

machine-function-info-after-pei.ll

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

machine-function-info-dynlds-align-invalid-case.mir

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machine-function-info-long-branch-reg-debug.ll

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

machine-function-info-long-branch-reg.ll

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

machine-function-info-no-ir.mir

Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) (#112492)

2024-10-21 13:44:09 +05:30

machine-function-info-register-parse-error1.mir

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machine-function-info-register-parse-error2.mir

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machine-function-info.ll

Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"

2024-11-08 20:21:16 -05:00

machine-metadata-error.mir

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

machine-metadata.mir

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mfi-frame-offset-reg-class.mir

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mfi-parse-error-frame-offset-reg.mir

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mfi-parse-error-scratch-rsrc-reg.mir

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mfi-parse-error-stack-ptr-offset-reg.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

mfi-scratch-rsrc-reg-reg-class.mir

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mfi-stack-ptr-offset-reg-class.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

mir-canon-multi.mir

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mircanon-memoperands.mir

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noconvergent-invalid.mir

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noconvergent.mir

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parse-order-reserved-regs.mir

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sgpr-for-exec-copy-invalid-reg.mir

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spill-phys-vgprs-invalid.mir

[AMDGPU][MIR] Serialize SpillPhysVGPRs (#113129)

2024-11-05 13:17:25 +05:30

spill-phys-vgprs-not-a-reg.mir

[AMDGPU][MIR] Serialize SpillPhysVGPRs (#113129)

2024-11-05 13:17:25 +05:30

spill-phys-vgprs.mir

[AMDGPU] Fix 3495d04 MIR test (#114963)

2024-11-05 17:11:47 +05:30

stack-id-assert.mir

[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001)

2024-03-18 10:37:59 -04:00

stack-id.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

subreg-def-is-not-ssa.mir

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syncscopes.mir

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

target-flags.mir

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target-index-operands.mir

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target-memoperands.mir

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vgpr-for-agpr-copy-invalid-reg.mir

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virtreg-uses-unallocatable-class.mir

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wwm-reserved-regs-invalid-reg.mir

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wwm-reserved-regs-not-a-reg.mir

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wwm-reserved-regs.mir

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