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fd3907ccb583df99e9c19d2fe84e4e7c52d75de9
clang-p2996
/
llvm
/
test
/
CodeGen
/
MIR
/
AMDGPU
History
Shilei Tian
6548b6354d
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (
#112403
)"
...
This reverts commit
ca33649abe
.
2024-11-08 20:21:16 -05:00
..
custom-pseudo-source-values.ll
…
dead-flag-on-use-operand-parse-error.mir
…
empty-custom-regmask.mir
…
expected-target-index-name.mir
…
intrinsics.mir
…
invalid-frame-index2.mir
…
invalid-frame-index-invalid-fixed-stack.mir
…
invalid-frame-index-invalid-stack.mir
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invalid-frame-index-no-stack.mir
…
invalid-frame-index.mir
…
invalid-target-index-operand.mir
…
killed-flag-on-def-parse-error.mir
…
lit.local.cfg
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llc-target-cpu-attr-from-cmdline-ir.mir
…
llc-target-cpu-attr-from-cmdline.mir
…
long-branch-reg-all-sgpr-used.ll
Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (
#108512
)
2024-09-13 11:54:30 +02:00
machine-function-info-after-pei.ll
Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (
#108512
)
2024-09-13 11:54:30 +02:00
machine-function-info-dynlds-align-invalid-case.mir
…
machine-function-info-long-branch-reg-debug.ll
Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (
#108512
)
2024-09-13 11:54:30 +02:00
machine-function-info-long-branch-reg.ll
Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (
#108512
)
2024-09-13 11:54:30 +02:00
machine-function-info-no-ir.mir
Reland [AMDGPU] Serialize WWM_REG vreg flag (
#110229
) (
#112492
)
2024-10-21 13:44:09 +05:30
machine-function-info-register-parse-error1.mir
…
machine-function-info-register-parse-error2.mir
…
machine-function-info.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (
#112403
)"
2024-11-08 20:21:16 -05:00
machine-metadata-error.mir
…
machine-metadata.mir
…
mfi-frame-offset-reg-class.mir
…
mfi-parse-error-frame-offset-reg.mir
…
mfi-parse-error-scratch-rsrc-reg.mir
…
mfi-parse-error-stack-ptr-offset-reg.mir
…
mfi-scratch-rsrc-reg-reg-class.mir
…
mfi-stack-ptr-offset-reg-class.mir
…
mir-canon-multi.mir
…
mircanon-memoperands.mir
…
noconvergent-invalid.mir
…
noconvergent.mir
…
parse-order-reserved-regs.mir
…
sgpr-for-exec-copy-invalid-reg.mir
…
spill-phys-vgprs-invalid.mir
[AMDGPU][MIR] Serialize SpillPhysVGPRs (
#113129
)
2024-11-05 13:17:25 +05:30
spill-phys-vgprs-not-a-reg.mir
[AMDGPU][MIR] Serialize SpillPhysVGPRs (
#113129
)
2024-11-05 13:17:25 +05:30
spill-phys-vgprs.mir
[AMDGPU] Fix
3495d04
MIR test (
#114963
)
2024-11-05 17:11:47 +05:30
stack-id-assert.mir
…
stack-id.mir
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subreg-def-is-not-ssa.mir
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syncscopes.mir
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target-flags.mir
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target-index-operands.mir
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target-memoperands.mir
…
vgpr-for-agpr-copy-invalid-reg.mir
…
virtreg-uses-unallocatable-class.mir
…
wwm-reserved-regs-invalid-reg.mir
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wwm-reserved-regs-not-a-reg.mir
…
wwm-reserved-regs.mir
…