b71386a4a4
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
106 lines
2.0 KiB
LLVM
106 lines
2.0 KiB
LLVM
; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 < %s -o - | FileCheck %s
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define i64 @dext_add_zext(i32 signext %n) {
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entry:
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%add = add i32 %n, 1
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%res = zext i32 %add to i64
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ret i64 %res
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; CHECK-LABEL: dext_add_zext:
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; CHECK: dext $[[R0:[0-9]+]], $[[R0:[0-9]+]], 0, 32
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}
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define i32 @ext_and24(i32 signext %a) {
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entry:
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%and = and i32 %a, 16777215
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ret i32 %and
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; CHECK-LABEL: ext_and24:
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; CHECK: ext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 24
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}
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define i64 @dext_and32(i64 zeroext %a) {
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entry:
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%and = and i64 %a, 4294967295
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ret i64 %and
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; CHECK-LABEL: dext_and32:
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; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32
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}
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define i64 @dext_and35(i64 zeroext %a) {
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entry:
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%and = and i64 %a, 34359738367
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ret i64 %and
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; CHECK-LABEL: dext_and35:
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; CHECK: dextm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 35
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}
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define i64 @dext_and20(i64 zeroext %a) {
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entry:
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%and = and i64 %a, 1048575
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ret i64 %and
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; CHECK-LABEL: dext_and20:
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; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 20
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}
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define i64 @dext_and16(i64 zeroext %a) {
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entry:
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%and = and i64 %a, 65535
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ret i64 %and
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; CHECK-LABEL: dext_and16:
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; CHECK: andi $[[R0:[0-9]+]], $[[R1:[0-9]+]], 65535
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}
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define i64 @dext_lsr_and20(i64 zeroext %a) {
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entry:
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%shr = lshr i64 %a, 5
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%and = and i64 %shr, 1048575
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ret i64 %and
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; CHECK-LABEL: dext_lsr_and20:
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; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 5, 20
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}
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define i64 @dext_lsr_and8(i64 zeroext %a) {
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entry:
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%shr = lshr i64 %a, 40
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%and = and i64 %shr, 255
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ret i64 %and
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; CHECK-LABEL: dext_lsr_and8:
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; CHECK: dextu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 40, 8
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}
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define i64 @dext_zext(i32 signext %a) {
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entry:
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%conv = zext i32 %a to i64
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ret i64 %conv
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; CHECK-LABEL: dext_zext:
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; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32
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}
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define i64 @dext_and_lsr(i64 zeroext %n) {
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entry:
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%and = lshr i64 %n, 8
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%shr = and i64 %and, 4095
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ret i64 %shr
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; CHECK-LABEL: dext_and_lsr:
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; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 8, 12
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}
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