eac743d1b0
MSA registers share the FPRs as its bottom half. So that we can use MSA
instructions to work with normal float/double:
double a, b, c;
asm volatile ("fmadd.d %w0, %w1, %w2" : "+f"(a) : "f"(b), "f"(c));
GCC has support it for quite long time.
51 lines
1.6 KiB
LLVM
51 lines
1.6 KiB
LLVM
; A basic inline assembly test
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; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
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@v4i32_r = global <4 x i32> zeroinitializer, align 16
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define void @test1() nounwind {
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entry:
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; CHECK-LABEL: test1:
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%0 = call <4 x i32> asm "ldi.w ${0:w}, 1", "=f"()
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; CHECK: ldi.w $w{{[1-3]?[0-9]}}, 1
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store <4 x i32> %0, ptr @v4i32_r
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ret void
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}
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define void @test2() nounwind {
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entry:
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; CHECK-LABEL: test2:
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%0 = load <4 x i32>, ptr @v4i32_r
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%1 = call <4 x i32> asm "addvi.w ${0:w}, ${1:w}, 1", "=f,f"(<4 x i32> %0)
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; CHECK: addvi.w $w{{[1-3]?[0-9]}}, $w{{[1-3]?[0-9]}}, 1
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store <4 x i32> %1, ptr @v4i32_r
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ret void
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}
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define void @test3() nounwind {
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entry:
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; CHECK-LABEL: test3:
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%0 = load <4 x i32>, ptr @v4i32_r
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%1 = call <4 x i32> asm sideeffect "addvi.w ${0:w}, ${1:w}, 1", "=f,f,~{$w0}"(<4 x i32> %0)
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; CHECK: addvi.w $w{{([1-9]|[1-3][0-9])}}, $w{{([1-9]|[1-3][0-9])}}, 1
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store <4 x i32> %1, ptr @v4i32_r
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ret void
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}
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define dso_local double @test4(double noundef %a, double noundef %b, double noundef %c) {
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entry:
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; CHECK-LABEL: test4:
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%0 = tail call double asm sideeffect "fmadd.d ${0:w}, ${1:w}, ${2:w}", "=f,f,f,0,~{$1}"(double %b, double %c, double %a)
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; CHECK: fmadd.d $w{{([0-9]|[1-3][0-9])}}, $w{{([0-9]|[1-3][0-9])}}, $w{{([0-9]|[1-3][0-9])}}
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ret double %0
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}
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define dso_local float @test5(float noundef %a, float noundef %b, float noundef %c) {
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entry:
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; CHECK-LABEL: test5:
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%0 = tail call float asm sideeffect "fmadd.w ${0:w}, ${1:w}, ${2:w}", "=f,f,f,0,~{$1}"(float %b, float %c, float %a)
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; CHECK: fmadd.w $w{{([0-9]|[1-3][0-9])}}, $w{{([0-9]|[1-3][0-9])}}, $w{{([0-9]|[1-3][0-9])}}
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ret float %0
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}
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