Durgadoss R 40d0058e6a [NVPTX] Add TMA bulk tensor reduction intrinsics (#116854) ...

This patch adds NVVM intrinsics and NVPTX codegen for:
* cp.async.bulk.tensor.reduce.1D -> 5D variants, supporting both Tile
   and Im2Col modes.
* These intrinsics optionally support cache_hints as indicated by the
   boolean flag argument.
* Lit tests are added for all combinations of these intrinsics in
   cp-async-bulk-tensor-reduce.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.

PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor

Signed-off-by: Durgadoss R <durgadossr@nvidia.com>

2024-11-27 10:57:51 +05:30

..

access-non-generic.ll

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activemask.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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add-sub-128bit.ll

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addr-mode.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

addrspacecast-gvar.ll

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addrspacecast.ll

[SDISel] Teach the type legalizer about ADDRSPACECAST (#90969)

2024-05-07 11:08:33 +02:00

aggr-param.ll

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aggregate-return.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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alias-errors.ll

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alias.ll

[NVPTX] Add support for calling aliases (#81170)

2024-02-08 17:14:13 -06:00

annotations.ll

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anonymous-fn-param.ll

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APIntLoadStore.ll

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APIntParam.ll

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APIntSextParam.ll

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APIntZextParam.ll

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arg-lowering.ll

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arithmetic-fp-sm20.ll

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arithmetic-int.ll

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async-copy.ll

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atomic-lower-local.ll

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atomicrmw-expand.ll

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atomics-sm60.ll

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atomics-sm70.ll

Reapply "AtomicExpand: Allow incrementally legalizing atomicrmw" (#107307)

2024-09-06 18:37:34 +04:00

atomics-sm90.ll

Reapply "AtomicExpand: Allow incrementally legalizing atomicrmw" (#107307)

2024-09-06 18:37:34 +04:00

atomics-with-scope.ll

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atomics.ll

Reland "[NVPTX] Add support for atomic add for f16 type" (#85197)

2024-03-15 08:13:59 +01:00

b52037.ll

[Tests] Drop inrange attribute from some tests (NFC)

2024-03-13 11:49:16 +01:00

barrier.ll

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bf16-instructions.ll

Revert "[NVPTX] Add folding for cvt.rn.bf16x2.f32" (#116376)

2024-11-15 13:04:51 +00:00

bf16.ll

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bf16x2-instructions-approx.ll

[NVPTX][NFC] Regenerate some tests checks (#116605)

2024-11-18 18:35:44 +00:00

bf16x2-instructions.ll

[NVPTX][NFC] Regenerate some tests checks (#116605)

2024-11-18 18:35:44 +00:00

bfe.ll

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boolean-patterns.ll

[NVPTX] improve Boolean ISel (#80166)

2024-01-31 14:37:27 -08:00

branch-fold.ll

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branch-fold.mir

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brkpt.ll

[LLVM][NVPTX] Add support for brkpt instruction (#104470)

2024-08-17 10:00:24 +05:30

bswap.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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bug17709.ll

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bug21465.ll

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bug22246.ll

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bug22322.ll

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bug26185-2.ll

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bug26185.ll

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bug41651.ll

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bug52623.ll

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bypass-div.ll

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call_bitcast_byval.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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call-with-alloca-buffer.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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callchain.ll

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calling-conv.ll

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calls-with-phi.ll

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chain-different-as.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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cluster-dim.ll

[NVPTX] Support !"cluster_dim_{x,y,z}" metadata (#109548)

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cmpxchg.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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combine-mad.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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combine-min-max.ll

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common-linkage.ll

Reland "[NVPTX] Use .common linkage for common globals" (#86824)

2024-03-29 11:58:41 -07:00

compare-int.ll

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compute-ptx-value-vts.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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constant-vectors.ll

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convergent-mir-call.ll

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convert-call-to-indirect.ll

[NVPTX] Verify ptx in the right version

2024-09-17 10:40:21 +02:00

convert-fp.ll

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convert-int-sm20.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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convert-sm80.ll

Revert "[NVPTX] Add folding for cvt.rn.bf16x2.f32" (#116376)

2024-11-15 13:04:51 +00:00

convert-sm89.ll

[NVPTX] Add conversion intrinsics from/to fp8 types (e4m3, e5m2) (#102969)

2024-08-19 10:34:22 -07:00

copysign.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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cp-async-bulk-tensor-g2s.ll

[NVPTX] Add TMA bulk tensor copy intrinsics (#96083)

2024-11-07 15:21:53 +05:30

cp-async-bulk-tensor-prefetch.ll

[NVPTX] Add TMA bulk tensor prefetch intrinsics (#115527)

2024-11-10 13:44:42 +05:30

cp-async-bulk-tensor-reduce.ll

[NVPTX] Add TMA bulk tensor reduction intrinsics (#116854)

2024-11-27 10:57:51 +05:30

cp-async-bulk-tensor-s2g.ll

[NVPTX] Add TMA bulk tensor copy intrinsics (#96083)

2024-11-07 15:21:53 +05:30

ctlz.ll

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ctpop.ll

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cttz.ll

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dag-cse.ll

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demote-vars.ll

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disable-opt.ll

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div-ri.ll

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div.ll

[LLVM][NVPTX] Add support for div.full instruction (#116482)

2024-11-27 04:57:42 +05:30

divrem-combine.ll

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dot-product.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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dynamic_stackalloc.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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dynamic-stackalloc-regression.ll

[NVPTX] Emit NVPTXISD::DYNAMIC_STACKALLOC's chain (#101714)

2024-08-05 10:53:33 -07:00

elect.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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empty-type.ll

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envreg.ll

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extloadv.ll

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extractelement.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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f16-abs.ll

[NVPTX] Add support for f16 fabs (#116107)

2024-11-18 13:47:08 -08:00

f16-ex2.ll

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f16-instructions.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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f16x2-instructions.ll

[NVPTX][NFC] Regenerate some tests checks (#116605)

2024-11-18 18:35:44 +00:00

fast-math.ll

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fcos-no-fast-math.ll

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fence-proxy-tensormap.ll

[LLVM][NVPTX] Add NVPTX codegen support for fence.proxy.tensormap (#100748)

2024-08-07 20:25:45 +05:30

fence-sm-90.ll

[NVPTX] Load/Store/Fence syncscope support (#106101)

2024-09-23 10:18:00 -07:00

fence.ll

[NVPTX] Load/Store/Fence syncscope support (#106101)

2024-09-23 10:18:00 -07:00

filetype-null.ll

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flo.ll

[NVPTX] Add support for nvvm.flo.[us] intrinsics (#114489)

2024-11-01 16:35:43 -07:00

fma-assoc.ll

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fma-disable.ll

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fma-relu-contract.ll

[NVPTX] Add patterns for fma.relu.{f16|f16x2|bf16|bf16x2} (#114977)

2024-11-18 15:29:17 +00:00

fma-relu-fma-intrinsic.ll

[NVPTX] Add patterns for fma.relu.{f16|f16x2|bf16|bf16x2} (#114977)

2024-11-18 15:29:17 +00:00

fma-relu-instruction-flag.ll

[NVPTX] Add patterns for fma.relu.{f16|f16x2|bf16|bf16x2} (#114977)

2024-11-18 15:29:17 +00:00

fma.ll

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fminimum-fmaximum.ll

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fns.ll

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fp16.ll

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fp-contract.ll

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fp-literals.ll

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fsin-no-fast-math.ll

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function-align.ll

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funnel-shift-clamp.ll

[NVPTX] Add support for clamped funnel shift intrinsics (#113228)

2024-10-22 16:39:44 -07:00

generic-to-nvvm-ir.ll

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generic-to-nvvm.ll

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global-addrspace.ll

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global-ctor-empty.ll

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global-ctor.ll

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global-dtor.ll

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global-incomplete-init.ll

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global-ordering.ll

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global-variable-big.ll

[test] Fix check prefixes

2024-05-13 14:01:00 -07:00

global-visibility.ll

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globals_init.ll

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globals_lowering.ll

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gvar-init.ll

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half.ll

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i1-array-global.ll

Fix i1 array global crash in NVPTXAsmPrinter. (#92506)

2024-05-17 12:06:35 +02:00

i1-ext-load.ll

[NVPTX] fix emission for i1 load and extload (#99392)

2024-07-18 10:29:24 -07:00

i1-global.ll

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i1-int-to-fp.ll

[NVPTX] Fix ISel patterns for i1 sint_to_fp (#110866)

2024-10-08 17:48:25 +01:00

i1-load-lower.ll

[NVPTX] fix emission for i1 load and extload (#99392)

2024-07-18 10:29:24 -07:00

i1-param.ll

Enable .ptr .global .align attributes for kernel attributes for CUDA (#114874)

2024-11-15 12:40:53 +00:00

i8-param.ll

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i8x2-instructions.ll

[NVPTX][NFC] Regenerate some tests checks (#116605)

2024-11-18 18:35:44 +00:00

i8x4-instructions.ll

Reland "[NVPTX] Emit prmt selection value in hex" (#115952)

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i16x2-instructions.ll

[NVPTX][NFC] Regenerate some tests checks (#116605)

2024-11-18 18:35:44 +00:00

i128-global.ll

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i128-param.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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i128-retval.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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i128-struct.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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i128.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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idioms.ll

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imad.ll

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indirect_byval.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

inline-asm-b128-test1.ll

[NVPTX] Update 32-bit NVPTX tests to use 64-bit

2024-07-10 16:01:12 -05:00

inline-asm-b128-test2.ll

[NVPTX] Update 32-bit NVPTX tests to use 64-bit

2024-07-10 16:01:12 -05:00

inline-asm-b128-test3.ll

[NVPTX] Update 32-bit NVPTX tests to use 64-bit

2024-07-10 16:01:12 -05:00

inline-asm.ll

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inlineasm-output-template.ll

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intr-range.ll

[NVPTX] Revamp NVVMIntrRange pass (#94422)

2024-06-06 06:42:46 -07:00

intrinsic-old.ll

[NVPTX] Revamp NVVMIntrRange pass (#94422)

2024-06-06 06:42:46 -07:00

intrinsics-sm90.ll

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intrinsics.ll

[LLVM] Add __builtin_readsteadycounter intrinsic and builtin for realtime clocks (#81331)

2024-02-13 10:06:25 -06:00

isspacep.ll

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jump-table.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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kernel-param-align.ll

Enable .ptr .global .align attributes for kernel attributes for CUDA (#114874)

2024-11-15 12:40:53 +00:00

ld-addrspace.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

ld-generic.ll

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ld-st-addrrspace.py

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ldg-invariant.ll

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ldparam-v4.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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ldu-i8.ll

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ldu-ldg.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

ldu-reg-plus-offset.ll

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lit.local.cfg

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load-sext-i1.ll

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load-store-sm-70.ll

[NVPTX] Load/Store/Fence syncscope support (#106101)

2024-09-23 10:18:00 -07:00

load-store-sm-90.ll

[NVPTX] Load/Store/Fence syncscope support (#106101)

2024-09-23 10:18:00 -07:00

load-store.ll

Reland "[NVPTX] Emit prmt selection value in hex" (#115952)

2024-11-12 19:21:34 -08:00

load-with-non-coherent-cache.ll

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LoadStoreVectorizer.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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local-stack-frame.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

loop-vectorize.ll

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lower-aggr-copies.ll

[LowerMemIntrinsics] Lower llvm.memmove to wide memory accesses (#100122)

2024-07-26 08:43:30 +02:00

lower-alloca.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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lower-args-gridconstant.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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lower-args.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

lower-byval-args.ll

[NVPTX] add an optional early copy of byval arguments (#113384)

2024-10-24 12:00:56 -07:00

lower-ctor-dtor.ll

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lower-kernel-ptr-arg.ll

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machine-sink.ll

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MachineSink-call.ll

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MachineSink-convergent.ll

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managed.ll

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match.ll

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math-intrins-sm53-ptx42.ll

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math-intrins-sm80-ptx70-autoupgrade.ll

[NVPTX][NFC] Update tests to use bfloat type (#101493)

2024-08-09 13:59:56 -07:00

math-intrins-sm80-ptx70-instcombine.ll

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math-intrins-sm80-ptx70.ll

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math-intrins-sm86-ptx72-autoupgrade.ll

[NVPTX][NFC] Update tests to use bfloat type (#101493)

2024-08-09 13:59:56 -07:00

math-intrins-sm86-ptx72.ll

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math-intrins.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

max-align.ll

[NVPTX] cap param alignment at 128 (max supported by ptx) (#96117)

2024-06-25 10:04:45 -07:00

maxclusterrank.ll

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mbarrier.ll

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minmax-negative.ll

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misaligned-vector-ldst.ll

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misched_func_call.ll

[llvm][NVPTX] Don't reorder MIs that construct a PTX function call (#116522)

2024-11-18 17:12:19 -05:00

mma-no-sink-after-laneid-check.ll

[NVPTX] Make nvptx mma instructions convergent. (#96521)

2024-06-24 22:15:58 -04:00

module-inline-asm.ll

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mulhi-intrins.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

mulwide.ll

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naked-fn-with-frame-pointer.ll

[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)

2024-10-18 09:35:42 +04:00

named-barriers.ll

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nanosleep.ll

[NVPTX] pass correct GPU arch to ptxas test (#81535)

2024-02-12 13:18:08 -08:00

no-extra-parens.ll

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noduplicate-syncthreads.ll

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nofunc.ll

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noreturn.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

nounroll.ll

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nvcl-param-align.ll

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nvptx-aa.ll

[NVPTX][AA] Traverse use-def chain to find non-generic addrspace (#106477)

2024-08-29 21:26:58 -07:00

nvvm-annotations-D120129.ll

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nvvm-reflect-arch-O0.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

nvvm-reflect-arch.ll

[NVVMReflect][Reland] Force dead branch elimination in NVVMReflect (#81189)

2024-02-08 20:09:44 -06:00

nvvm-reflect-module-flag.ll

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nvvm-reflect-ocl.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

nvvm-reflect-opaque.ll

[NVPTX] Add clang builtin for __nvvm_reflect intrinsic (#81277)

2024-02-09 14:11:01 -06:00

nvvm-reflect.ll

[NVPTX] Add clang builtin for __nvvm_reflect intrinsic (#81277)

2024-02-09 14:11:01 -06:00

packed-aggr.ll

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param-align.ll

[NVPTX] Don't use underlying alignment to align param (#96793)

2024-06-27 10:19:05 +01:00

param-load-store.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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param-overalign.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

param-vectorize-device.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

param-vectorize-kernel.ll

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pass-name.ll

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pow2_mask_cmp.ll

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pr13291-i1-store.ll

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pr16278.ll

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pr17529.ll

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proxy-reg-erasure-ptx.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

proxy-reg-erasure.mir

[llvm][NVPTX] Fix RAUW bug in NVPTXProxyRegErasure (#105871)

2024-08-24 13:19:44 -04:00

rcp-opt.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

read-global-variable-constant.ll

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redux-sync.ll

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refl1.ll

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reg-copy.ll

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reg-types.ll

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rotate_64.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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rotate.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

rsqrt-opt.ll

[NVPTX] Improve support for rsqrt.approx (#89417)

2024-04-23 08:56:39 -07:00

rsqrt.ll

[NVPTX] Improve support for rsqrt.approx (#89417)

2024-04-23 08:56:39 -07:00

sad-intrins.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

sched1.ll

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sched2.ll

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setmaxnreg.ll

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sext-in-reg.ll

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sext-params.ll

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sext-setcc.ll

Reland "[NVPTX] Emit prmt selection value in hex" (#115952)

2024-11-12 19:21:34 -08:00

shfl-p.ll

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shfl-sync-p.ll

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shfl-sync.ll

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shfl.ll

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shift-parts.ll

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short-ptr.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

shuffle-vec-undef-init.ll

Reland "[NVPTX] Emit prmt selection value in hex" (#115952)

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simple-call.ll

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sm-version.ll

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speculative-execution-divergent-target.ll

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sqrt-approx.ll

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st-addrspace.ll

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

st-generic.ll

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st-param-imm.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

stacksaverestore.ll

[NVPTX] Add support for stacksave, stackrestore intrinsics (#114484)

2024-11-01 13:26:28 -07:00

store-retval.ll

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store-undef.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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surf-read-cuda.ll

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surf-read.ll

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surf-tex.py

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surf-write-cuda.ll

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surf-write.ll

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symbol-naming.ll

[NVPTX] improve identifier renaming for PTX (#79459)

2024-01-26 13:49:00 -08:00

TailDuplication-convergent.ll

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tex-read-cuda.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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tex-read.ll

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texsurf-queries.ll

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tid-range.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

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unaligned-param-load-store.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

unfold-masked-merge-vector-variablemask.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

unreachable.ll

[NVPTX] Only run LowerUnreachable when necessary (#109868)

2024-10-10 12:57:43 -07:00

vaargs.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

variadics-backend.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

variadics-lowering.ll

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

2024-11-06 11:53:33 +00:00

vec8.ll

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vec-param-load.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

vector-args.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

vector-call.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

vector-compare.ll

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vector-global.ll

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vector-loads.ll

[NVPTX] Emit ld.v4.b16 for loading <4 x bfloat> (#109069)

2024-09-17 21:06:46 -07:00

vector-returns.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

vector-select.ll

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vector-stores.ll

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vectorize-misaligned.ll

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vote.ll

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weak-global.ll

Reland "[NVPTX] Use .common linkage for common globals" (#86824)

2024-03-29 11:58:41 -07:00

weak-linkage.ll

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wmma-ptx60-sm70.py

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wmma-ptx61-sm70.py

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wmma-ptx63-sm72.py

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wmma-ptx63-sm75.py

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wmma-ptx64-sm70.py

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wmma-ptx65-sm75.py

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wmma-ptx71-sm80.py

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wmma.py

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zeroext-32bit.ll

[test] Convert text files from CRLF to LF

2024-05-03 10:09:52 -07:00