228f88fdc8
This change implements support for the `cr` and `cf` register constraints (which allocate a RVC GPR or RVC FPR respectively), and the `N` modifier (which prints the raw encoding of a register rather than the name). The intention behind these additions is to make it easier to use inline assembly when assembling raw instructions that are not supported by the compiler, for instance when experimenting with new instructions or when supporting proprietary extensions outside the toolchain. These implement part of my proposal in riscv-non-isa/riscv-c-api-doc#92 As part of the implementation, I felt there was not enough coverage of inline assembly and the "in X" floating-point extensions, so I have added more regression tests around these configurations.
327 lines
8.7 KiB
LLVM
327 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -no-integrated-as < %s \
|
|
; RUN: | FileCheck -check-prefix=RV32I %s
|
|
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -no-integrated-as < %s \
|
|
; RUN: | FileCheck -check-prefix=RV64I %s
|
|
|
|
@gi = external global i32
|
|
|
|
define i32 @constraint_r(i32 %a) nounwind {
|
|
; RV32I-LABEL: constraint_r:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a1, %hi(gi)
|
|
; RV32I-NEXT: lw a1, %lo(gi)(a1)
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: add a0, a0, a1
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: constraint_r:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a1, %hi(gi)
|
|
; RV64I-NEXT: lw a1, %lo(gi)(a1)
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: add a0, a0, a1
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = load i32, ptr @gi
|
|
%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
|
|
ret i32 %2
|
|
}
|
|
|
|
; Don't allow 'x0' for 'r'. Some instructions have a different behavior when
|
|
; x0 is encoded.
|
|
define i32 @constraint_r_zero(i32 %a) nounwind {
|
|
; RV32I-LABEL: constraint_r_zero:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, %hi(gi)
|
|
; RV32I-NEXT: lw a0, %lo(gi)(a0)
|
|
; RV32I-NEXT: li a1, 0
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: add a0, a1, a0
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: constraint_r_zero:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a0, %hi(gi)
|
|
; RV64I-NEXT: lw a0, %lo(gi)(a0)
|
|
; RV64I-NEXT: li a1, 0
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: add a0, a1, a0
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = load i32, ptr @gi
|
|
%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 0, i32 %1)
|
|
ret i32 %2
|
|
}
|
|
|
|
define i32 @constraint_cr(i32 %a) nounwind {
|
|
; RV32I-LABEL: constraint_cr:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a1, %hi(gi)
|
|
; RV32I-NEXT: lw a1, %lo(gi)(a1)
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: c.add a0, a0, a1
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: constraint_cr:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a1, %hi(gi)
|
|
; RV64I-NEXT: lw a1, %lo(gi)(a1)
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: c.add a0, a0, a1
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = load i32, ptr @gi
|
|
%2 = tail call i32 asm "c.add $0, $1, $2", "=^cr,0,^cr"(i32 %a, i32 %1)
|
|
ret i32 %2
|
|
}
|
|
|
|
define i32 @constraint_i(i32 %a) nounwind {
|
|
; RV32I-LABEL: constraint_i:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: addi a0, a0, 113
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: constraint_i:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: addi a0, a0, 113
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = load i32, ptr @gi
|
|
%2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
|
|
ret i32 %2
|
|
}
|
|
|
|
define void @constraint_I() nounwind {
|
|
; RV32I-LABEL: constraint_I:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: addi a0, a0, 2047
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: addi a0, a0, -2048
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: constraint_I:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: addi a0, a0, 2047
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: addi a0, a0, -2048
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 2047)
|
|
tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 -2048)
|
|
ret void
|
|
}
|
|
|
|
define void @constraint_J() nounwind {
|
|
; RV32I-LABEL: constraint_J:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: addi a0, a0, 0
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: constraint_J:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: addi a0, a0, 0
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
tail call void asm sideeffect "addi a0, a0, $0", "J"(i32 0)
|
|
ret void
|
|
}
|
|
|
|
define void @constraint_K() nounwind {
|
|
; RV32I-LABEL: constraint_K:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: csrwi mstatus, 31
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: csrwi mstatus, 0
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: constraint_K:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: csrwi mstatus, 31
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: csrwi mstatus, 0
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 31)
|
|
tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 0)
|
|
ret void
|
|
}
|
|
|
|
define i32 @modifier_z_zero(i32 %a) nounwind {
|
|
; RV32I-LABEL: modifier_z_zero:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: add a0, a0, zero
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: modifier_z_zero:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: add a0, a0, zero
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,i"(i32 %a, i32 0)
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @modifier_z_nonzero(i32 %a) nounwind {
|
|
; RV32I-LABEL: modifier_z_nonzero:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: add a0, a0, 1
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: modifier_z_nonzero:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: add a0, a0, 1
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,i"(i32 %a, i32 1)
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @modifier_i_imm(i32 %a) nounwind {
|
|
; RV32I-LABEL: modifier_i_imm:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: addi a0, a0, 1
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: modifier_i_imm:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 1)
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @modifier_i_reg(i32 %a, i32 %b) nounwind {
|
|
; RV32I-LABEL: modifier_i_reg:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: add a0, a0, a1
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: modifier_i_reg:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: add a0, a0, a1
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 %b)
|
|
ret i32 %1
|
|
}
|
|
|
|
;; `.insn 0x4, 0x33 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is the
|
|
;; raw encoding of `add`
|
|
|
|
define i32 @modifier_N_reg(i32 %a, i32 %b) nounwind {
|
|
; RV32I-LABEL: modifier_N_reg:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: .insn 0x4, 0x33 | (10 << 7) | (10 << 15) | (11 << 20)
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: modifier_N_reg:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: .insn 0x4, 0x33 | (10 << 7) | (10 << 15) | (11 << 20)
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = tail call i32 asm ".insn 0x4, 0x33 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=r,r,r"(i32 %a, i32 %b)
|
|
ret i32 %1
|
|
}
|
|
|
|
;; `.insn 0x2, 0x9422 | (${0:N} << 7) | (${2:N} << 2)` is the raw encoding of
|
|
;; `c.add` (note the constraint that the first input should be the same as the
|
|
;; output).
|
|
|
|
define i32 @modifier_N_with_cr_reg(i32 %a, i32 %b) nounwind {
|
|
; RV32I-LABEL: modifier_N_with_cr_reg:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: .insn 0x2, 0x9422 | (10 << 7) | (11 << 2)
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: modifier_N_with_cr_reg:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: .insn 0x2, 0x9422 | (10 << 7) | (11 << 2)
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
%1 = tail call i32 asm ".insn 0x2, 0x9422 | (${0:N} << 7) | (${2:N} << 2)", "=^cr,0,^cr"(i32 %a, i32 %b)
|
|
ret i32 %1
|
|
}
|
|
|
|
define void @operand_global() nounwind {
|
|
; RV32I-LABEL: operand_global:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: .8byte gi
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: operand_global:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: .8byte gi
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: ret
|
|
tail call void asm sideeffect ".8byte $0", "i"(ptr @gi)
|
|
ret void
|
|
}
|
|
|
|
define void @operand_block_address() nounwind {
|
|
; RV32I-LABEL: operand_block_address:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: #APP
|
|
; RV32I-NEXT: j .Ltmp0
|
|
; RV32I-NEXT: #NO_APP
|
|
; RV32I-NEXT: .Ltmp0: # Block address taken
|
|
; RV32I-NEXT: # %bb.1: # %bb
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: operand_block_address:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: #APP
|
|
; RV64I-NEXT: j .Ltmp0
|
|
; RV64I-NEXT: #NO_APP
|
|
; RV64I-NEXT: .Ltmp0: # Block address taken
|
|
; RV64I-NEXT: # %bb.1: # %bb
|
|
; RV64I-NEXT: ret
|
|
call void asm sideeffect "j $0", "i"(ptr blockaddress(@operand_block_address, %bb))
|
|
br label %bb
|
|
bb:
|
|
ret void
|
|
}
|
|
|
|
; TODO: expand tests for more complex constraints, out of range immediates etc
|