67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
65 lines
2.1 KiB
LLVM
65 lines
2.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; CHECK-DAG: OpName [[FOOBAR:%.+]] "foobar"
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; CHECK-DAG: OpName [[PRODUCER:%.+]] "producer"
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; CHECK-DAG: OpName [[CONSUMER:%.+]] "consumer"
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; CHECK-NOT: DAG-FENCE
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%ty1 = type {i16, i32}
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%ty2 = type {%ty1, i64}
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; CHECK-DAG: [[I16:%.+]] = OpTypeInt 16
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; CHECK-DAG: [[I32:%.+]] = OpTypeInt 32
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; CHECK-DAG: [[I64:%.+]] = OpTypeInt 64
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; CHECK-DAG: [[TY1:%.+]] = OpTypeStruct [[I16]] [[I32]]
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; CHECK-DAG: [[TY2:%.+]] = OpTypeStruct [[TY1]] [[I64]]
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; CHECK-DAG: [[UNDEF_I16:%.+]] = OpUndef [[I16]]
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; CHECK-DAG: [[UNDEF_I64:%.+]] = OpUndef [[I64]]
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; CHECK-DAG: [[UNDEF_TY2:%.+]] = OpUndef [[TY2]]
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; CHECK-DAG: [[CST_42:%.+]] = OpConstant [[I32]] 42
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; CHECK-NOT: DAG-FENCE
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define i32 @foobar() {
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%agg = call %ty2 @producer(i16 undef, i32 42, i64 undef)
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%ret = call i32 @consumer(%ty2 %agg)
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ret i32 %ret
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}
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; CHECK: [[FOOBAR]] = OpFunction
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; CHECK: [[AGG:%.+]] = OpFunctionCall [[TY2]] [[PRODUCER]] [[UNDEF_I16]] [[CST_42]] [[UNDEF_I64]]
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; CHECK: [[RET:%.+]] = OpFunctionCall [[I32]] [[CONSUMER]] [[AGG]]
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; CHECK: OpReturnValue [[RET]]
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; CHECK: OpFunctionEnd
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define %ty2 @producer(i16 %a, i32 %b, i64 %c) {
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%agg1 = insertvalue %ty2 undef, i16 %a, 0, 0
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%agg2 = insertvalue %ty2 %agg1, i32 %b, 0, 1
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%agg3 = insertvalue %ty2 %agg2, i64 %c, 1
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ret %ty2 %agg3
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}
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; CHECK: [[PRODUCER]] = OpFunction
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; CHECK: [[A:%.+]] = OpFunctionParameter [[I16]]
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; CHECK: [[B:%.+]] = OpFunctionParameter [[I32]]
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; CHECK: [[C:%.+]] = OpFunctionParameter [[I64]]
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; CHECK: [[AGG1:%.+]] = OpCompositeInsert [[TY2]] [[A]] [[UNDEF_TY2]] 0 0
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; CHECK: [[AGG2:%.+]] = OpCompositeInsert [[TY2]] [[B]] [[AGG1]] 0 1
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; CHECK: [[AGG3:%.+]] = OpCompositeInsert [[TY2]] [[C]] [[AGG2]] 1
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; CHECK: OpReturnValue [[AGG3]]
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; CHECK: OpFunctionEnd
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define i32 @consumer(%ty2 %agg) {
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%ret = extractvalue %ty2 %agg, 0, 1
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ret i32 %ret
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}
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; CHECK: [[CONSUMER]] = OpFunction
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; CHECK: [[AGG:%.+]] = OpFunctionParameter [[TY2]]
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; CHECK: [[RET:%.+]] = OpCompositeExtract [[I32]] [[AGG]] 0 1
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; CHECK: OpReturnValue [[RET]]
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; CHECK: OpFunctionEnd
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