[bazel] Port c474f8f240

utils/bazel/llvm-project-overlay/clang/BUILD.bazel

@@ -258,6 +258,12 @@ td_library(
     includes = ["include"],
 )
 
+td_library(
+    name = "BuiltinsSPIRVBaseTdFiles",
+    srcs = ["include/clang/Basic/BuiltinsSPIRVBase.td"],
+    includes = ["include"],
+)
+
 td_library(
     name = "BuiltinsRISCVXCVTdFiles",
     srcs = ["include/clang/Basic/BuiltinsRISCVXCV.td"],
@@ -303,11 +309,36 @@ gentbl_cc_library(
 )
 
 gentbl_cc_library(
-    name = "basic_builtins_spirv_gen",
-    tbl_outs = {"include/clang/Basic/BuiltinsSPIRV.inc": ["-gen-clang-builtins"]},
+    name = "basic_builtins_spirv_cl_gen",
+    tbl_outs = {"include/clang/Basic/BuiltinsSPIRVCL.inc": ["-gen-clang-builtins"]},
     tblgen = ":clang-tblgen",
-    td_file = "include/clang/Basic/BuiltinsSPIRV.td",
-    deps = [":BuiltinsBaseTdFiles"],
+    td_file = "include/clang/Basic/BuiltinsSPIRVCL.td",
+    deps = [
+        ":BuiltinsBaseTdFiles",
+        ":BuiltinsSPIRVBaseTdFiles",
+    ],
+)
+
+gentbl_cc_library(
+    name = "basic_builtins_spirv_common_gen",
+    tbl_outs = {"include/clang/Basic/BuiltinsSPIRVCommon.inc": ["-gen-clang-builtins"]},
+    tblgen = ":clang-tblgen",
+    td_file = "include/clang/Basic/BuiltinsSPIRVCommon.td",
+    deps = [
+        ":BuiltinsBaseTdFiles",
+        ":BuiltinsSPIRVBaseTdFiles",
+    ],
+)
+
+gentbl_cc_library(
+    name = "basic_builtins_spirv_vk_gen",
+    tbl_outs = {"include/clang/Basic/BuiltinsSPIRVVK.inc": ["-gen-clang-builtins"]},
+    tblgen = ":clang-tblgen",
+    td_file = "include/clang/Basic/BuiltinsSPIRVVK.td",
+    deps = [
+        ":BuiltinsBaseTdFiles",
+        ":BuiltinsSPIRVBaseTdFiles",
+    ],
 )
 
 gentbl_cc_library(
@@ -656,7 +687,9 @@ cc_library(
         ":basic_builtins_hexagon_gen",
         ":basic_builtins_nvptx_gen",
         ":basic_builtins_riscv_gen",
-        ":basic_builtins_spirv_gen",
+        ":basic_builtins_spirv_cl_gen",
+        ":basic_builtins_spirv_common_gen",
+        ":basic_builtins_spirv_vk_gen",
         ":basic_builtins_x86_64_gen",
         ":basic_builtins_x86_gen",
         ":basic_riscv_andes_vector_builtins_gen",