[AMDGPU] Refactor FLAT_Load_Pseudo class (#146539)
NFC. Refactor it to make it easier to inherit from.
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@@ -208,21 +208,26 @@ class GlobalSaddrTable <bit is_saddr, string Name = ""> {
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// TODO: Is exec allowed for saddr? The disabled value 0x7f is the
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// same encoding value as exec_hi, so it isn't possible to use that if
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// saddr is 32-bit (which isn't handled here yet).
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class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
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bit HasTiedOutput = 0,
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bit HasSaddr = 0, bit EnableSaddr = 0,
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RegisterOperand vdata_op = getLdStRegisterOperand<regClass>.ret> : FLAT_Pseudo<
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opName,
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(outs vdata_op:$vdst),
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!con(
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class FLAT_Load_Pseudo<
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string opName, RegisterClass regClass, bit HasTiedOutput = 0,
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bit HasSaddr = 0, bit EnableSaddr = 0>
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: FLAT_Pseudo<opName, (outs), (ins), ""> {
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defvar vdata_op = getLdStRegisterOperand<regClass>.ret;
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let OutOperandList = (outs vdata_op:$vdst);
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let InOperandList = !con(
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!if(EnableSaddr,
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(ins SReg_64_XEXEC_XNULL:$saddr, VGPR_32:$vaddr),
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(ins VReg_64:$vaddr)),
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(ins flat_offset:$offset),
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// FIXME: Operands with default values do not work with following non-optional operands.
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!if(HasTiedOutput, (ins CPol:$cpol, vdata_op:$vdst_in),
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(ins CPol_0:$cpol))),
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" $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$cpol"> {
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(ins SReg_64_XEXEC_XNULL:$saddr, VGPR_32:$vaddr),
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(ins VReg_64:$vaddr)),
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(ins flat_offset:$offset),
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// FIXME: Operands with default values do not work with following
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// non-optional operands.
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!if(HasTiedOutput, (ins CPol:$cpol, vdata_op:$vdst_in),
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(ins CPol_0:$cpol)));
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let AsmOperands = " $vdst, $vaddr"
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# !if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")
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# "$offset$cpol";
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let has_data = 0;
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let mayLoad = 1;
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let has_saddr = HasSaddr;
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