[CodeGen] Use Register in SwitchLoweringUtils. NFC (#109092)
Use an empty Register() instead of -1U.
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@@ -170,7 +170,7 @@ struct CaseBlock {
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struct JumpTable {
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/// The virtual register containing the index of the jump table entry
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/// to jump to.
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unsigned Reg;
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Register Reg;
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/// The JumpTableIndex for this jump table in the function.
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unsigned JTI;
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/// The MBB into which to emit the code for the indirect jump.
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@@ -182,7 +182,7 @@ struct JumpTable {
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/// The debug location of the instruction this JumpTable was produced from.
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std::optional<SDLoc> SL; // For SelectionDAG
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JumpTable(unsigned R, unsigned J, MachineBasicBlock *M, MachineBasicBlock *D,
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JumpTable(Register R, unsigned J, MachineBasicBlock *M, MachineBasicBlock *D,
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std::optional<SDLoc> SL)
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: Reg(R), JTI(J), MBB(M), Default(D), SL(SL) {}
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};
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@@ -218,7 +218,7 @@ struct BitTestBlock {
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APInt First;
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APInt Range;
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const Value *SValue;
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unsigned Reg;
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Register Reg;
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MVT RegVT;
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bool Emitted;
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bool ContiguousRange;
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@@ -229,7 +229,7 @@ struct BitTestBlock {
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BranchProbability DefaultProb;
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bool FallthroughUnreachable = false;
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BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT, bool E,
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BitTestBlock(APInt F, APInt R, const Value *SV, Register Rg, MVT RgVT, bool E,
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bool CR, MachineBasicBlock *P, MachineBasicBlock *D,
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BitTestInfo C, BranchProbability Pr)
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: First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg),
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@@ -838,7 +838,7 @@ void IRTranslator::splitWorkItem(SwitchCG::SwitchWorkList &WorkList,
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void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
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MachineBasicBlock *MBB) {
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// Emit the code for the jump table
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assert(JT.Reg != -1U && "Should lower JT Header first!");
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assert(JT.Reg && "Should lower JT Header first!");
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MachineIRBuilder MIB(*MBB->getParent());
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MIB.setMBB(*MBB);
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MIB.setDebugLoc(CurBuilder->getDebugLoc());
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@@ -2981,7 +2981,7 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
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void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) {
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// Emit the code for the jump table
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assert(JT.SL && "Should set SDLoc for SelectionDAG!");
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assert(JT.Reg != -1U && "Should lower JT Header first!");
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assert(JT.Reg && "Should lower JT Header first!");
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EVT PTy = DAG.getTargetLoweringInfo().getJumpTableRegTy(DAG.getDataLayout());
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SDValue Index = DAG.getCopyFromReg(getControlRoot(), *JT.SL, JT.Reg, PTy);
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SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
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@@ -3261,10 +3261,9 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
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/// visitBitTestCase - this function produces one "bit test"
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void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
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MachineBasicBlock* NextMBB,
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MachineBasicBlock *NextMBB,
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BranchProbability BranchProbToNext,
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unsigned Reg,
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BitTestCase &B,
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Register Reg, BitTestCase &B,
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MachineBasicBlock *SwitchBB) {
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SDLoc dl = getCurSDLoc();
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MVT VT = BB.RegVT;
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@@ -526,7 +526,7 @@ public:
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void visitBitTestHeader(SwitchCG::BitTestBlock &B,
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MachineBasicBlock *SwitchBB);
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void visitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB,
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BranchProbability BranchProbToNext, unsigned Reg,
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BranchProbability BranchProbToNext, Register Reg,
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SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB);
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void visitJumpTable(SwitchCG::JumpTable &JT);
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void visitJumpTableHeader(SwitchCG::JumpTable &JT,
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@@ -254,7 +254,7 @@ bool SwitchCG::SwitchLowering::buildJumpTable(const CaseClusterVector &Clusters,
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->createJumpTableIndex(Table);
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// Set up the jump table info.
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JumpTable JT(-1U, JTI, JumpTableMBB, nullptr, SL);
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JumpTable JT(Register(), JTI, JumpTableMBB, nullptr, SL);
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JumpTableHeader JTH(Clusters[First].Low->getValue(),
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Clusters[Last].High->getValue(), SI->getCondition(),
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nullptr, false);
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@@ -455,7 +455,7 @@ bool SwitchCG::SwitchLowering::buildBitTests(CaseClusterVector &Clusters,
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BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
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}
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BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
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SI->getCondition(), -1U, MVT::Other, false,
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SI->getCondition(), Register(), MVT::Other, false,
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ContiguousRange, nullptr, nullptr, std::move(BTI),
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TotalProb);
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