caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[llvm] Remove br i1 undef from CodeGen/X86 tests (#121733)

Browse Source 
This PR removes tests with `br i1 undef` under `llvm/tests/CodeGen/X86`.
There will be more PRs in the future for this directory.

Replacing `undef` with a new function argument doesn't work in some of
the tests, instead, I've replaced them with `poison`.
This commit is contained in:
Lee Wei
2025-01-06 01:43:39 -07:00
committed by GitHub
parent f99b190757
commit 2b63077cfa
44 changed files with 238 additions and 243 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/test/CodeGen/X86/2011-06-03-x87chain.ll
View File

@@ -30,9 +30,9 @@ entry:
ret float %conv
}
define void @PR17495() {
define void @PR17495(i1 %arg) {
entry:
br i1 undef, label %while.end, label %while.body
br i1 %arg, label %while.end, label %while.body
while.body: ; preds = %while.body, %entry
%x.1.copyload = load i24, ptr undef, align 1

8
llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll
View File

@@ -165,7 +165,7 @@ failure: ; preds = %backedge
unreachable
}
define void @test_04() {
define void @test_04(i32 %arg) {
; CHECK-LABEL: test_04:
; CHECK: ## %bb.0: ## %bb
; CHECK-NEXT: ud2
@@ -175,7 +175,7 @@ bb:
bb1: ; preds = %bb10, %bb
%tmp = phi i64 [ 1, %bb ], [ %tmp2, %bb10 ]
%tmp2 = add nuw nsw i64 %tmp, 1
br i1 undef, label %bb21, label %bb7
br i1 poison, label %bb21, label %bb7
bb7: ; preds = %bb1
%tmp8 = add nsw i64 %tmp, -1
@@ -187,7 +187,7 @@ bb10: ; preds = %bb16
br label %bb1
bb11: ; preds = %bb16, %bb7
switch i32 undef, label %bb19 [
switch i32 %arg, label %bb19 [
i32 0, label %bb17
i32 1, label %bb16
i32 2, label %bb15
@@ -205,7 +205,7 @@ bb15: ; preds = %bb11
unreachable
bb16: ; preds = %bb11
br i1 undef, label %bb10, label %bb11
br i1 poison, label %bb10, label %bb11
bb17: ; preds = %bb11
unreachable

76
llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll
View File

@@ -5,13 +5,13 @@ define void @undef_2phi(ptr%buf) {
; CHECK-LABEL: @undef_2phi(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L2]], label [[L3:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[L3:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: br i1 undef, label [[L3]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L3]], label [[EXIT:%.*]]
; CHECK: l3:
; CHECK-NEXT: [[TMP2:%.*]] = phi x86_amx [ [[TMP1]], [[L2]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP2]])
@@ -20,16 +20,16 @@ define void @undef_2phi(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %l3
br i1 poison, label %l2, label %l3
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
br i1 undef, label %l3, label %exit
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
br i1 poison, label %l3, label %exit
l3:
%t4 = phi <256 x i32> [ %t3, %l2], [ %t2, %l1 ]
@@ -45,10 +45,10 @@ define void @foo_undef(ptr%buf) {
; CHECK-LABEL: @foo_undef(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP1]])
@@ -57,15 +57,15 @@ define void @foo_undef(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
%t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr %buf, i64 1024, x86_amx %t4)
br label %exit
@@ -78,10 +78,10 @@ define void @foo_zero(ptr%buf) {
; CHECK-LABEL: @foo_zero(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP1]])
@@ -90,12 +90,12 @@ define void @foo_zero(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ zeroinitializer, %entry ], [ %t2, %l1 ]
@@ -112,14 +112,14 @@ define void @foo_vrow(ptr%buf, i16 %row) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 [[ROW:%.*]], i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 32, ptr [[TMP1]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP3:%.*]] = load <256 x i32>, ptr [[TMP1]], align 1024
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP3]], [[L1]] ]
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ poison, [[ENTRY:%.*]] ], [ [[TMP3]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[TMP0]], align 1024
; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 [[ROW]], i16 32, ptr [[TMP0]], i64 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP5]])
@@ -128,15 +128,15 @@ define void @foo_vrow(ptr%buf, i16 %row) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
%t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
call void @llvm.x86.tilestored64.internal(i16 %row, i16 32, ptr %buf, i64 1024, x86_amx %t4)
br label %exit
@@ -150,13 +150,13 @@ define void @foo_vcol(ptr%buf, i16 %col) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 [[COL:%.*]])
; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[COL]] to i64
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 [[COL]], ptr [[TMP1]], i64 [[TMP3]], x86_amx [[T1]])
; CHECK-NEXT: [[TMP4:%.*]] = load <256 x i32>, ptr [[TMP1]], align 1024
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[TMP4]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[TMP0]], align 1024
@@ -168,12 +168,12 @@ define void @foo_vcol(ptr%buf, i16 %col) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 %col)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ zeroinitializer, %entry ], [ %t2, %l1 ]
@@ -189,29 +189,29 @@ define void @noshape(ptr%buf) {
; CHECK-LABEL: @noshape(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP2:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ poison, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[BUF:%.*]], align 1024
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
%t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
%t5 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t4)
store <256 x i32> %t5, ptr %buf
@@ -225,14 +225,14 @@ define void @noshape2(ptr%buf) {
; CHECK-LABEL: @noshape2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP2:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ poison, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: [[T6:%.*]] = call <256 x i32> @llvm.abs.v256i32(<256 x i32> [[T3]], i1 true)
; CHECK-NEXT: store <256 x i32> [[T6]], ptr [[BUF:%.*]], align 1024
; CHECK-NEXT: br label [[EXIT]]
@@ -240,15 +240,15 @@ define void @noshape2(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
%t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ]
%t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
%t5 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t4)
%t6 = call <256 x i32> @llvm.abs.v256i32(<256 x i32> %t5, i1 1)

62
llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll
View File

@@ -18,14 +18,14 @@ wrapper_entry:
; Cases where amxcast can be combined across bb
; %5 and %6 is combined together since %goodphi's incoming is phi or amxcast
define void @combine_amx_cast_and_phi() {
define void @combine_amx_cast_and_phi(i1 %arg) {
; CHECK-LABEL: @combine_amx_cast_and_phi(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <560 x i8>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <616 x i8>, align 64
; CHECK-NEXT: [[TMP2:%.*]] = alloca <110 x i32>, align 64
; CHECK-NEXT: [[TMP3:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK: for.body.i.lr.ph.i:
; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP2]], align 512
; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP2]], i64 40)
@@ -43,7 +43,7 @@ define void @combine_amx_cast_and_phi() {
wrapper_entry:
%0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
%tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0)
br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
for.body.i.lr.ph.i: ; preds = %wrapper_entry
%1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef)
@@ -62,7 +62,7 @@ for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i,
; Cases where amxcast can't be combined across bb
; %5 and %6 is not combined together since %evilphi's incoming is not phi or amxcast
define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp) {
define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp, i1 %arg) {
; CHECK-LABEL: @fail_to_combine_amx_cast_and_phi(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <110 x i32>, align 64
@@ -71,7 +71,7 @@ define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp) {
; CHECK-NEXT: [[TMP3:%.*]] = alloca <616 x i8>, align 64
; CHECK-NEXT: [[TMP4:%.*]] = alloca <110 x i32>, align 64
; CHECK-NEXT: [[TMP5:%.*]] = add <110 x i32> [[TMP:%.*]], [[TMP]]
; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK: for.body.i.lr.ph.i:
; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP4]], align 512
; CHECK-NEXT: [[TMP7:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP4]], i64 40)
@@ -92,7 +92,7 @@ define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp) {
;
wrapper_entry:
%0 = add <110 x i32> %tmp, %tmp
br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
for.body.i.lr.ph.i: ; preds = %wrapper_entry
%1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef)
@@ -111,7 +111,7 @@ for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i,
; Cases where amxcast can't be combined across bb
; %5 and %6 is not combined together since %evilphi's user aka %evilphi2 is not inside phi web.
define void @fail_to_combine_amx_cast_and_phi2() {
define void @fail_to_combine_amx_cast_and_phi2(i1 %arg) {
; CHECK-LABEL: @fail_to_combine_amx_cast_and_phi2(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <110 x i32>, align 64
@@ -123,7 +123,7 @@ define void @fail_to_combine_amx_cast_and_phi2() {
; CHECK-NEXT: [[TMP6:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr [[TMP5]], i64 40, x86_amx [[TMP6]])
; CHECK-NEXT: [[TMP8:%.*]] = load <110 x i32>, ptr [[TMP5]], align 512
; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK: for.body.i.lr.ph.i:
; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP4]], align 512
; CHECK-NEXT: [[TMP10:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP4]], i64 40)
@@ -134,13 +134,13 @@ define void @fail_to_combine_amx_cast_and_phi2() {
; CHECK-NEXT: [[TMP15:%.*]] = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx [[TMP10]], x86_amx [[TMP12]], x86_amx [[TMP14]])
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr [[TMP1]], i64 40, x86_amx [[TMP15]])
; CHECK-NEXT: [[TMP17:%.*]] = load <110 x i32>, ptr [[TMP1]], align 512
; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 [[ARG]], label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]]
; CHECK: for.cond.cleanup.i.i:
; CHECK-NEXT: [[GOODPHI:%.*]] = phi <110 x i32> [ [[TMP8]], [[WRAPPER_ENTRY:%.*]] ], [ [[TMP17]], [[FOR_BODY_I_LR_PH_I]] ]
; CHECK-NEXT: store <110 x i32> [[GOODPHI]], ptr [[TMP0]], align 512
; CHECK-NEXT: [[TMP19:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP0]], i64 40)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP19]])
; CHECK-NEXT: br i1 undef, label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]]
; CHECK-NEXT: br i1 [[ARG]], label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]]
; CHECK: exit:
; CHECK-NEXT: [[EVILPHI2:%.*]] = phi <110 x i32> [ [[GOODPHI]], [[FOR_COND_CLEANUP_I_I]] ], [ [[TMP17]], [[FOR_BODY_I_LR_PH_I]] ]
; CHECK-NEXT: store <110 x i32> [[EVILPHI2]], ptr undef, align 512
@@ -149,7 +149,7 @@ define void @fail_to_combine_amx_cast_and_phi2() {
wrapper_entry:
%0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
%tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0)
br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
for.body.i.lr.ph.i: ; preds = %wrapper_entry
%1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef)
@@ -157,27 +157,27 @@ for.body.i.lr.ph.i: ; preds = %wrapper_entry
%3 = call x86_amx @llvm.x86.cast.vector.to.tile.v560i8(<560 x i8> undef)
%4 = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx %1, x86_amx %2, x86_amx %3)
%5 = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %4)
br i1 undef, label %for.cond.cleanup.i.i, label %exit
br i1 %arg, label %for.cond.cleanup.i.i, label %exit
for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i, %wrapper_entry
%goodphi = phi <110 x i32> [ %tmp, %wrapper_entry ], [ %5, %for.body.i.lr.ph.i ]
%6 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %goodphi)
call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx %6)
br i1 undef, label %exit, label %for.body.i.lr.ph.i
br i1 %arg, label %exit, label %for.body.i.lr.ph.i
exit:
%evilphi2 = phi <110 x i32> [ %goodphi, %for.cond.cleanup.i.i ], [ %5, %for.body.i.lr.ph.i ]
store <110 x i32> %evilphi2, ptr undef, align 512
ret void
}
define void @fail_to_combine_amx_cast_and_phi_due_to_const_value() {
define void @fail_to_combine_amx_cast_and_phi_due_to_const_value(i1 %arg) {
; CHECK-LABEL: @fail_to_combine_amx_cast_and_phi_due_to_const_value(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <560 x i8>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <616 x i8>, align 64
; CHECK-NEXT: [[TMP2:%.*]] = alloca <110 x i32>, align 64
; CHECK-NEXT: [[TMP3:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 11, i16 40)
; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK: for.body.i.lr.ph.i:
; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP2]], align 512
; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP2]], i64 40)
@@ -193,7 +193,7 @@ define void @fail_to_combine_amx_cast_and_phi_due_to_const_value() {
; CHECK-NEXT: ret void
;
wrapper_entry:
br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
for.body.i.lr.ph.i: ; preds = %wrapper_entry
%0 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef)
@@ -213,14 +213,14 @@ for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i,
; Cases where amxcast can be combined across bb
; When optimizeAMXCastFromPhi process %6 and %goodphi, %goodphi2 is outside the phi-web, so the optimization stop
; When optimizeAMXCastFromPhi process %7 and %goodphi2, the optimization continue.
define void @combine_amx_cast_and_multiple_phi() {
define void @combine_amx_cast_and_multiple_phi(i1 %arg) {
; CHECK-LABEL: @combine_amx_cast_and_multiple_phi(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <560 x i8>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <616 x i8>, align 64
; CHECK-NEXT: [[TMP2:%.*]] = alloca <110 x i32>, align 64
; CHECK-NEXT: [[TMP3:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK: for.body.i.lr.ph.i:
; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP2]], align 512
; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP2]], i64 40)
@@ -229,11 +229,11 @@ define void @combine_amx_cast_and_multiple_phi() {
; CHECK-NEXT: store <560 x i8> undef, ptr [[TMP0]], align 1024
; CHECK-NEXT: [[TMP9:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 14, i16 40, ptr [[TMP0]], i64 40)
; CHECK-NEXT: [[TMP10:%.*]] = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx [[TMP5]], x86_amx [[TMP7]], x86_amx [[TMP9]])
; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 [[ARG]], label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]]
; CHECK: for.cond.cleanup.i.i:
; CHECK-NEXT: [[TMP11:%.*]] = phi x86_amx [ [[TMP3]], [[WRAPPER_ENTRY:%.*]] ], [ [[TMP10]], [[FOR_BODY_I_LR_PH_I]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP11]])
; CHECK-NEXT: br i1 undef, label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]]
; CHECK-NEXT: br i1 [[ARG]], label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]]
; CHECK: exit:
; CHECK-NEXT: [[TMP12:%.*]] = phi x86_amx [ [[TMP11]], [[FOR_COND_CLEANUP_I_I]] ], [ [[TMP10]], [[FOR_BODY_I_LR_PH_I]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP12]])
@@ -242,7 +242,7 @@ define void @combine_amx_cast_and_multiple_phi() {
wrapper_entry:
%0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
%tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0)
br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
for.body.i.lr.ph.i: ; preds = %wrapper_entry
%1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef)
@@ -250,13 +250,13 @@ for.body.i.lr.ph.i: ; preds = %wrapper_entry
%3 = call x86_amx @llvm.x86.cast.vector.to.tile.v560i8(<560 x i8> undef)
%4 = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx %1, x86_amx %2, x86_amx %3)
%5 = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %4)
br i1 undef, label %for.cond.cleanup.i.i, label %exit
br i1 %arg, label %for.cond.cleanup.i.i, label %exit
for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i, %wrapper_entry
%goodphi = phi <110 x i32> [ %tmp, %wrapper_entry ], [ %5, %for.body.i.lr.ph.i ]
%6 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %goodphi)
call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx %6)
br i1 undef, label %exit, label %for.body.i.lr.ph.i
br i1 %arg, label %exit, label %for.body.i.lr.ph.i
exit:
%evilphi2 = phi <110 x i32> [ %goodphi, %for.cond.cleanup.i.i ], [ %5, %for.body.i.lr.ph.i ]
%7 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %evilphi2)
@@ -265,7 +265,7 @@ exit:
}
; Currently we are not able to delete DeadPHICycle, later we will handle with them
define void @combine_amx_cast_and_phi_in_a_circle() {
define void @combine_amx_cast_and_phi_in_a_circle(i1 %arg) {
; CHECK-LABEL: @combine_amx_cast_and_phi_in_a_circle(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <110 x i32>, align 64
@@ -284,7 +284,7 @@ define void @combine_amx_cast_and_phi_in_a_circle() {
; CHECK-NEXT: [[TMP11:%.*]] = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx [[TMP6]], x86_amx [[TMP8]], x86_amx [[TMP10]])
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr [[TMP0]], i64 40, x86_amx [[TMP11]])
; CHECK-NEXT: [[TMP13:%.*]] = load <110 x i32>, ptr [[TMP0]], align 512
; CHECK-NEXT: br i1 undef, label [[BB2:%.*]], label [[BB3:%.*]]
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]
; CHECK: bb2:
; CHECK-NEXT: [[TMP14:%.*]] = phi x86_amx [ [[TMP15:%.*]], [[BB3]] ], [ [[TMP11]], [[BB1]] ]
; CHECK-NEXT: [[GOODPHI:%.*]] = phi <110 x i32> [ [[EVILPHI2:%.*]], [[BB3]] ], [ [[TMP13]], [[BB1]] ]
@@ -294,7 +294,7 @@ define void @combine_amx_cast_and_phi_in_a_circle() {
; CHECK-NEXT: [[TMP15]] = phi x86_amx [ [[TMP14]], [[BB2]] ], [ [[TMP11]], [[BB1]] ]
; CHECK-NEXT: [[EVILPHI2]] = phi <110 x i32> [ [[GOODPHI]], [[BB2]] ], [ [[TMP13]], [[BB1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP15]])
; CHECK-NEXT: br i1 undef, label [[BB2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 [[ARG]], label [[BB2]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP15]])
; CHECK-NEXT: ret void
@@ -310,7 +310,7 @@ bb1: ; preds = %wrapper_entry
%3 = call x86_amx @llvm.x86.cast.vector.to.tile.v560i8(<560 x i8> undef)
%4 = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx %1, x86_amx %2, x86_amx %3)
%5 = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %4)
br i1 undef, label %bb2, label %bb3
br i1 %arg, label %bb2, label %bb3
bb2: ; preds = %bb1, %wrapper_entry
%goodphi = phi <110 x i32> [ %evilphi2, %bb3], [ %5, %bb1 ]
@@ -321,19 +321,19 @@ bb3:
%evilphi2 = phi <110 x i32> [ %goodphi, %bb2 ], [ %5, %bb1 ]
%7 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %evilphi2)
call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx %7)
br i1 undef, label %bb2, label %exit
br i1 %arg, label %bb2, label %exit
exit:
%8 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %evilphi2)
call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx %8)
ret void
}
define void @eliminate_unused_phi_and_cast() {
define void @eliminate_unused_phi_and_cast(i1 %arg) {
; CHECK-LABEL: @eliminate_unused_phi_and_cast(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <560 x i8>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK: for.body.i.lr.ph.i:
; CHECK-NEXT: [[TMP2:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 56, ptr undef, i64 undef)
; CHECK-NEXT: [[TMP3:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 14, i16 40, ptr undef, i64 undef)
@@ -349,7 +349,7 @@ define void @eliminate_unused_phi_and_cast() {
wrapper_entry:
%0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
%tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0)
br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
for.body.i.lr.ph.i: ; preds = %wrapper_entry
%1 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 56, ptr undef, i64 undef)

10
llvm/test/CodeGen/X86/AMX/lat-transform-amx-bitcast.ll
View File

@@ -317,16 +317,16 @@ define dso_local void @__tile_stored(ptr %0, i64 %1, ptr nocapture readonly byva
ret void
}
define void @dead_code(ptr%buf) {
define void @dead_code(ptr%buf, i1 %arg) {
; CHECK-LABEL: @dead_code(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP1:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024
; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
; CHECK-NEXT: br i1 [[ARG]], label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP1]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[BUF:%.*]], align 1024
@@ -335,12 +335,12 @@ define void @dead_code(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
br i1 undef, label %l1, label %l2
br i1 %arg, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
br i1 undef, label %l2, label %exit
br i1 %arg, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]

2
llvm/test/CodeGen/X86/StackColoring.ll
View File

@@ -135,7 +135,7 @@ entry:
%t3 = call i32 @foo(i32 %in, ptr %a3)
%t4 = call i32 @foo(i32 %in, ptr %a3)
call void @llvm.lifetime.end.p0(i64 -1, ptr %a3)
br i1 undef, label %bb2, label %bb3
br i1 poison, label %bb2, label %bb3
bb2:
call void @llvm.lifetime.start.p0(i64 -1, ptr %a4)
%t11 = call i32 @foo(i32 %in, ptr %a4)

10
llvm/test/CodeGen/X86/asm-label.ll
View File

@@ -12,15 +12,15 @@
; SAVETEMP: jne {{.*}} <.LBB0_1>
; SAVETEMP-LABEL: <.LBB0_1>:
define void @foo() {
define void @foo(i1 %arg, i32 %arg2) {
entry:
br i1 undef, label %land.lhs.true, label %if.end11
br i1 %arg, label %land.lhs.true, label %if.end11
land.lhs.true: ; preds = %entry
br i1 undef, label %if.then, label %if.end11
br i1 %arg, label %if.then, label %if.end11
if.then: ; preds = %land.lhs.true
br i1 undef, label %if.then9, label %if.end
br i1 %arg, label %if.then9, label %if.end
if.then9: ; preds = %if.then
br label %cleanup
@@ -29,7 +29,7 @@ if.end: ; preds = %if.then
br label %cleanup
cleanup: ; preds = %if.end, %if.then9
switch i32 undef, label %default [
switch i32 %arg2, label %default [
i32 0, label %cleanup.cont
i32 1, label %if.end11
]

2
llvm/test/CodeGen/X86/avx-select.ll
View File

@@ -84,7 +84,7 @@ head:
%isneg = icmp slt <4 x i32> %v3, zeroinitializer
%or0 = select <4 x i1> %isneg, <4 x i32> <i32 26146, i32 -1257, i32 -2, i32 -3052>, <4 x i32> <i32 -24947, i32 7802, i32 29242, i32 15858>
%or1 = shufflevector <4 x i32> %or0, <4 x i32> <i32 29361, i32 -16094, i32 -3080, i32 -26286>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
br i1 undef, label %exit, label %head
br i1 poison, label %exit, label %head
exit:
store <8 x i32> %or1, ptr addrspace(1) undef, align 32

10
llvm/test/CodeGen/X86/avx512-i1test.ll
View File

@@ -21,20 +21,20 @@ define void @func() {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jmp .LBB0_2
bb1:
br i1 undef, label %L_10, label %L_10
br i1 poison, label %L_10, label %L_10
L_10: ; preds = %bb1, %bb1
br i1 undef, label %L_30, label %bb56
br i1 poison, label %L_30, label %bb56
bb56: ; preds = %L_10
br label %bb33
bb33: ; preds = %bb51, %bb56
%r111 = load i64, ptr undef, align 8
br i1 undef, label %bb51, label %bb35
br i1 poison, label %bb51, label %bb35
bb35: ; preds = %bb33
br i1 undef, label %L_19, label %bb37
br i1 poison, label %L_19, label %bb37
bb37: ; preds = %bb35
%r128 = and i64 %r111, 576460752303423488
@@ -43,7 +43,7 @@ bb37: ; preds = %bb35
L_19: ; preds = %bb37, %bb35
%"$V_S25.0" = phi i1 [ %phitmp, %bb37 ], [ true, %bb35 ]
br i1 undef, label %bb51, label %bb42
br i1 poison, label %bb51, label %bb42
bb42: ; preds = %L_19
%r136 = select i1 %"$V_S25.0", ptr undef, ptr undef

28
llvm/test/CodeGen/X86/block-placement.ll
View File

@@ -312,7 +312,7 @@ exit:
ret i32 %sum
}
define void @unnatural_cfg1() {
define void @unnatural_cfg1(i1 %arg) {
; Test that we can handle a loop with an inner unnatural loop at the end of
; a function. This is a gross CFG reduced out of the single source GCC.
; CHECK-LABEL: unnatural_cfg1
@@ -327,7 +327,7 @@ loop.header:
br label %loop.body1
loop.body1:
br i1 undef, label %loop.body3, label %loop.body2
br i1 %arg, label %loop.body3, label %loop.body2
loop.body2:
%ptr = load ptr, ptr undef, align 4
@@ -341,14 +341,14 @@ loop.body3:
br i1 %comp, label %loop.body4, label %loop.body5
loop.body4:
br i1 undef, label %loop.header, label %loop.body5
br i1 %arg, label %loop.header, label %loop.body5
loop.body5:
%ptr2 = load ptr, ptr undef, align 4
br label %loop.body3
}
define void @unnatural_cfg2(ptr %p0, i32 %a0) {
define void @unnatural_cfg2(ptr %p0, i32 %a0, i1 %arg) {
; Test that we can handle a loop with a nested natural loop *and* an unnatural
; loop. This was reduced from a crash on block placement when run over
; single-source GCC.
@@ -372,10 +372,10 @@ loop.header:
loop.body1:
%val0 = load ptr, ptr undef, align 4
br i1 undef, label %loop.body2, label %loop.inner1.begin
br i1 %arg, label %loop.body2, label %loop.inner1.begin
loop.body2:
br i1 undef, label %loop.body4, label %loop.body3
br i1 %arg, label %loop.body4, label %loop.body3
loop.body3:
%ptr1 = getelementptr inbounds i32, ptr %val0, i32 0
@@ -467,7 +467,7 @@ exit:
ret i32 %merge
}
define void @fpcmp_unanalyzable_branch(i1 %cond, double %a0) {
define void @fpcmp_unanalyzable_branch(i1 %cond, double %a0, i1 %arg) {
; This function's CFG contains an once-unanalyzable branch (une on floating
; points). As now it becomes analyzable, we should get best layout in which each
; edge in 'entry' -> 'entry.if.then_crit_edge' -> 'if.then' -> 'if.end' is
@@ -493,7 +493,7 @@ entry.if.then_crit_edge:
br label %if.then
lor.lhs.false:
br i1 undef, label %if.end, label %exit
br i1 %arg, label %if.end, label %exit
exit:
%cmp.i = fcmp une double 0.000000e+00, %a0
@@ -516,7 +516,7 @@ declare i32 @f()
declare i32 @g()
declare i32 @h(i32 %x)
define i32 @test_global_cfg_break_profitability() {
define i32 @test_global_cfg_break_profitability(i1 %arg) {
; Check that our metrics for the profitability of a CFG break are global rather
; than local. A successor may be very hot, but if the current block isn't, it
; doesn't matter. Within this test the 'then' block is slightly warmer than the
@@ -530,7 +530,7 @@ define i32 @test_global_cfg_break_profitability() {
; CHECK: ret
entry:
br i1 undef, label %then, label %else, !prof !2
br i1 %arg, label %then, label %else, !prof !2
then:
%then.result = call i32 @f()
@@ -600,7 +600,7 @@ cleanup:
unreachable
}
define void @test_unnatural_cfg_backwards_inner_loop() {
define void @test_unnatural_cfg_backwards_inner_loop(i1 %arg) {
; Test that when we encounter an unnatural CFG structure after having formed
; a chain for an inner loop which happened to be laid out backwards we don't
; attempt to merge onto the wrong end of the inner loop just because we find it
@@ -612,7 +612,7 @@ define void @test_unnatural_cfg_backwards_inner_loop() {
; CHECK: %loop3
entry:
br i1 undef, label %loop2a, label %body
br i1 %arg, label %loop2a, label %body
body:
br label %loop2a
@@ -692,7 +692,7 @@ exit:
ret void
}
define void @unanalyzable_branch_to_free_block(float %x) {
define void @unanalyzable_branch_to_free_block(float %x, i1 %arg) {
; Ensure that we can handle unanalyzable branches where the destination block
; gets selected as the best free block in the CFG.
;
@@ -704,7 +704,7 @@ define void @unanalyzable_branch_to_free_block(float %x) {
; CHECK: %exit
entry:
br i1 undef, label %a, label %b
br i1 %arg, label %a, label %b
a:
call i32 @f()

3
llvm/test/CodeGen/X86/clobber_frame_ptr.ll
View File

@@ -173,7 +173,7 @@ define ghccc void @test5() {
; CHECK-NEXT: .cfi_def_cfa %rsp, 8
; CHECK-NEXT: jmp tail@PLT # TAILCALL
entry:
br i1 undef, label %then, label %else
br i1 poison, label %then, label %else
then:
store i64 0, ptr undef
@@ -186,4 +186,3 @@ else:
exit:
ret void
}

6
llvm/test/CodeGen/X86/codegen-prepare-replacephi.mir
View File

@@ -6,7 +6,7 @@
# "Replacement PHI node is already replaced."
--- |
define void @f1() {
define void @f1(i1 %arg) {
entry:
%arrayidx = getelementptr inbounds [2 x i16], ptr undef, i16 0, i16 2
br label %for.cond
@@ -30,10 +30,10 @@
%5 = phi ptr [ %4, %for.body ], [ %5, %if.then5 ], [ undef, %for.cond2 ]
%6 = phi ptr [ %3, %for.body ], [ %6, %if.then5 ], [ undef, %for.cond2 ]
%7 = phi ptr [ %2, %for.body ], [ %6, %if.then5 ], [ undef, %for.cond2 ]
br i1 undef, label %for.cond2, label %if.then5
br i1 %arg, label %for.cond2, label %if.then5
if.then5:
br i1 undef, label %cleanup, label %for.cond2
br i1 %arg, label %cleanup, label %for.cond2
cleanup:
br i1 true, label %for.cond, label %for.body

6
llvm/test/CodeGen/X86/codegen-prepare-replacephi2.mir
View File

@@ -7,7 +7,7 @@
--- |
define void @f1() {
define void @f1(i1 %arg) {
entry:
%arrayidx = getelementptr inbounds [2 x i16], ptr undef, i16 0, i16 2
br label %for.cond
@@ -24,7 +24,7 @@
%2 = phi ptr [ %1, %for.cond ], [ %12, %cleanup ]
%3 = phi ptr [ %0, %for.cond ], [ %11, %cleanup ]
%4 = phi ptr [ %0, %for.cond ], [ %10, %cleanup ]
br i1 undef, label %for.cond2.preheader, label %if.then
br i1 %arg, label %for.cond2.preheader, label %if.then
for.cond2.preheader:
br label %for.cond2
@@ -37,7 +37,7 @@
%5 = phi ptr [ %8, %for.inc ], [ %4, %for.cond2.preheader ]
%6 = phi ptr [ %9, %for.inc ], [ %3, %for.cond2.preheader ]
%7 = phi ptr [ %9, %for.inc ], [ %2, %for.cond2.preheader ]
br i1 undef, label %for.inc, label %if.then5
br i1 %arg, label %for.inc, label %if.then5
if.then5:
br i1 true, label %cleanup.loopexit, label %if.end

2
llvm/test/CodeGen/X86/combine-concatvectors.ll
View File

@@ -72,7 +72,7 @@ alloca_0:
br label %loop.4942
loop.4942: ; preds = %loop.4942, %alloca_0
br i1 undef, label %loop.4942, label %ifmerge.1298
br i1 poison, label %loop.4942, label %ifmerge.1298
ifmerge.1298: ; preds = %loop.4942
%gepload4638 = load float, ptr getelementptr inbounds ([49216 x i8], ptr @qa_, i64 0, i64 28324), align 4

48
llvm/test/CodeGen/X86/crash.ll
View File

@@ -115,9 +115,9 @@ do.body92: ; preds = %if.then66
; Crash during XOR optimization.
; <rdar://problem/7869290>
define void @test7() nounwind ssp {
define void @test7(i1 %arg) nounwind ssp {
entry:
br i1 undef, label %bb14, label %bb67
br i1 %arg, label %bb14, label %bb67
bb14:
%tmp0 = trunc i16 undef to i1
@@ -157,14 +157,14 @@ entry:
; shift of and.
%struct.S0 = type { i8, [2 x i8], i8 }
define void @func_59(i32 %p_63) noreturn nounwind {
define void @func_59(i32 %p_63, i1 %arg) noreturn nounwind {
entry:
br label %for.body
for.body: ; preds = %for.inc44, %entry
%p_63.addr.1 = phi i32 [ %p_63, %entry ], [ 0, %for.inc44 ]
%l_74.0 = phi i32 [ 0, %entry ], [ %add46, %for.inc44 ]
br i1 undef, label %for.inc44, label %bb.nph81
br i1 %arg, label %for.inc44, label %bb.nph81
bb.nph81: ; preds = %for.body
%tmp98 = add i32 %p_63.addr.1, 0
@@ -237,7 +237,7 @@ declare i64 @llvm.objectsize.i64.p0(ptr, i1) nounwind readnone
%t20 = type { i32, i32 }
%t21 = type { ptr }
define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 {
define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE(i1 %arg) ssp align 2 {
bb:
%tmp = load ptr, ptr undef, align 4
%tmp3 = getelementptr inbounds %t9, ptr %tmp, i32 0, i32 0, i32 0, i32 0, i32 1
@@ -246,7 +246,7 @@ bb:
bb4: ; preds = %bb37, %bb
%tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ]
%tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ]
br i1 undef, label %bb34, label %bb7
br i1 %arg, label %bb34, label %bb7
bb7: ; preds = %bb4
%tmp8 = load i32, ptr undef, align 4
@@ -292,7 +292,7 @@ bb33: ; preds = %bb29
unreachable
bb34: ; preds = %bb4
br i1 undef, label %bb36, label %bb35
br i1 %arg, label %bb36, label %bb35
bb35: ; preds = %bb34
store ptr null, ptr %tmp3, align 4
@@ -319,7 +319,7 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind
; PR10463
; Spilling a virtual register with <undef> uses.
define void @autogen_239_1000() {
define void @autogen_239_1000(i1 %arg) {
BB:
%Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef>
br label %CF
@@ -327,14 +327,14 @@ BB:
CF:
%B16 = frem <8 x double> zeroinitializer, %Shuff
%E19 = extractelement <8 x double> %Shuff, i32 5
br i1 undef, label %CF, label %CF75
br i1 %arg, label %CF, label %CF75
CF75:
br i1 undef, label %CF75, label %CF76
br i1 %arg, label %CF75, label %CF76
CF76:
store double %E19, ptr undef
br i1 undef, label %CF76, label %CF77
br i1 %arg, label %CF76, label %CF77
CF77:
%B55 = fmul <8 x double> %B16, undef
@@ -396,24 +396,24 @@ if.end:
; InstrEmitter::EmitSubregNode() may steal virtual registers from already
; emitted blocks when isCoalescableExtInstr points out the opportunity.
; Make sure kill flags are cleared on the newly global virtual register.
define i64 @ov_read(ptr %vf, ptr nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, ptr %bitstream) nounwind uwtable ssp {
define i64 @ov_read(ptr %vf, ptr nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, ptr %bitstream, i1 %arg) nounwind uwtable ssp {
entry:
br i1 undef, label %return, label %while.body.preheader
br i1 %arg, label %return, label %while.body.preheader
while.body.preheader: ; preds = %entry
br i1 undef, label %if.then3, label %if.end7
br i1 %arg, label %if.then3, label %if.end7
if.then3: ; preds = %while.body.preheader
%0 = load i32, ptr undef, align 4
br i1 undef, label %land.lhs.true.i255, label %if.end7
br i1 %arg, label %land.lhs.true.i255, label %if.end7
land.lhs.true.i255: ; preds = %if.then3
br i1 undef, label %if.then.i256, label %if.end7
br i1 %arg, label %if.then.i256, label %if.end7
if.then.i256: ; preds = %land.lhs.true.i255
%sub.i = sub i32 0, %0
%conv = sext i32 %sub.i to i64
br i1 undef, label %if.end7, label %while.end
br i1 %arg, label %if.end7, label %while.end
if.end7: ; preds = %if.then.i256, %land.lhs.true.i255, %if.then3, %while.body.preheader
unreachable
@@ -486,12 +486,12 @@ declare void @fn3(...)
; When coalescing %1 and %2, the IMPLICIT_DEF instruction should be
; erased along with its value number.
;
define void @rdar12474033() nounwind ssp {
define void @rdar12474033(i1 %arg, i32 %arg2, i32 %arg3, i32 %arg4) nounwind ssp {
bb:
br i1 undef, label %bb21, label %bb1
br i1 %arg, label %bb21, label %bb1
bb1: ; preds = %bb
switch i32 undef, label %bb10 [
switch i32 %arg2, label %bb10 [
i32 4, label %bb2
i32 1, label %bb9
i32 5, label %bb3
@@ -503,7 +503,7 @@ bb2: ; preds = %bb1
unreachable
bb3: ; preds = %bb1, %bb1
br i1 undef, label %bb4, label %bb5
br i1 %arg, label %bb4, label %bb5
bb4: ; preds = %bb3
unreachable
@@ -521,7 +521,7 @@ bb9: ; preds = %bb1, %bb1
bb10: ; preds = %bb5, %bb1
%tmp11 = phi i128 [ undef, %bb1 ], [ %tmp6, %bb5 ]
%tmp12 = phi i128 [ 0, %bb1 ], [ %tmp8, %bb5 ]
switch i32 undef, label %bb21 [
switch i32 %arg3, label %bb21 [
i32 2, label %bb18
i32 3, label %bb13
i32 5, label %bb16
@@ -530,7 +530,7 @@ bb10: ; preds = %bb5, %bb1
]
bb13: ; preds = %bb10
br i1 undef, label %bb15, label %bb14
br i1 %arg, label %bb15, label %bb14
bb14: ; preds = %bb13
br label %bb21
@@ -554,7 +554,7 @@ bb21: ; preds = %bb18, %bb14, %bb10,
%tmp23 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp19, %bb18 ]
store <4 x float> %tmp23, ptr undef, align 16
store <4 x float> %tmp22, ptr undef, align 16
switch i32 undef, label %bb29 [
switch i32 %arg4, label %bb29 [
i32 5, label %bb27
i32 1, label %bb24
i32 2, label %bb25

4
llvm/test/CodeGen/X86/domain-reassignment-test.ll
View File

@@ -3,7 +3,7 @@
; Check that the X86 domain reassignment pass doesn't introduce an illegal
; test instruction. See PR37396
define void @japi1_foo2_34617() {
define void @japi1_foo2_34617(i1 %arg) {
pass2:
br label %if5
@@ -27,7 +27,7 @@ if5:
%tmp120 = and i1 %tmp118, %tmp119
%tmp121 = zext i1 %tmp120 to i8
%tmp122 = and i8 %b.055, %tmp121
br i1 undef, label %L174, label %if5
br i1 %arg, label %L174, label %if5
L188:
unreachable

4
llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
View File

@@ -5,9 +5,9 @@
; The machine verifier will catch and complain about this case.
; CHECK-LABEL: baz
; CHECK: retq
define void @baz() {
define void @baz(i1 %arg) {
entry:
br i1 undef, label %exit, label %exit
br i1 %arg, label %exit, label %exit
exit:
ret void

6
llvm/test/CodeGen/X86/fold-vector-shuffle-crash.ll
View File

@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7
define void @autogen_SD13708(i32) {
define void @autogen_SD13708(i32, i1 %arg) {
BB:
%Shuff7 = shufflevector <8 x i32> zeroinitializer, <8 x i32> zeroinitializer, <8 x i32> <i32 8, i32 10, i32 12, i32 14, i32 undef, i32 2, i32 4, i32 undef>
br label %CF
@@ -8,11 +8,11 @@ BB:
CF:
%Tr = trunc <8 x i64> zeroinitializer to <8 x i32>
%Shuff20 = shufflevector <8 x i32> %Shuff7, <8 x i32> %Tr, <8 x i32> <i32 13, i32 15, i32 1, i32 3, i32 5, i32 7, i32 undef, i32 11>
br i1 undef, label %CF, label %CF247
br i1 %arg, label %CF, label %CF247
CF247:
%I171 = insertelement <8 x i32> %Shuff20, i32 %0, i32 0
br i1 undef, label %CF, label %CF247
br i1 %arg, label %CF, label %CF247
}
define void @autogen_SD13800(ptr, ptr, ptr, i32, i64, i8) {

12
llvm/test/CodeGen/X86/hoist-spill.ll
View File

@@ -14,7 +14,7 @@ target triple = "x86_64-unknown-linux-gnu"
@d = external global ptr, align 8
; Function Attrs: norecurse noreturn nounwind uwtable
define void @fn1(i32 %p1, i32 %p2, i64 %p3) {
define void @fn1(i32 %p1, i32 %p2, i64 %p3, i1 %arg) {
entry:
%tmp = load ptr, ptr @d, align 8
%tmp1 = load ptr, ptr @a, align 8
@@ -54,10 +54,10 @@ for.cond4.preheader: ; preds = %for.body, %for.cond
br i1 %cmp528, label %for.inc14, label %for.body6.preheader
for.body6.preheader: ; preds = %for.cond4.preheader
br i1 undef, label %for.body6, label %min.iters.checked
br i1 %arg, label %for.body6, label %min.iters.checked
min.iters.checked: ; preds = %for.body6.preheader
br i1 undef, label %for.body6, label %vector.memcheck
br i1 %arg, label %for.body6, label %vector.memcheck
vector.memcheck: ; preds = %min.iters.checked
%bound1 = icmp ule ptr undef, %scevgep41
@@ -85,10 +85,10 @@ vector.body: ; preds = %vector.body, %vecto
%tmp16 = getelementptr inbounds i32, ptr %tmp1, i64 %offset.idx.1
store <4 x i32> %wide.load.1, ptr %tmp16, align 4
%index.next.3 = add i64 %index, 32
br i1 undef, label %middle.block, label %vector.body
br i1 %arg, label %middle.block, label %vector.body
middle.block: ; preds = %vector.body, %vector.body.preheader.split
br i1 undef, label %for.inc14, label %for.body6
br i1 %arg, label %for.inc14, label %for.body6
for.body.preheader: ; preds = %for.cond
br label %for.body
@@ -98,7 +98,7 @@ for.body: ; preds = %for.body, %for.body
%add = add nsw i32 %k.127, 1
%tmp18 = load i32, ptr undef, align 4
store i32 %tmp18, ptr @b, align 4
br i1 undef, label %for.body, label %for.cond4.preheader
br i1 %arg, label %for.body, label %for.cond4.preheader
for.body6: ; preds = %for.body6, %middle.block, %vector.memcheck, %min.iters.checked, %for.body6.preheader
%indvars.iv32 = phi i64 [ undef, %for.body6 ], [ %tmp12, %vector.memcheck ], [ %tmp12, %min.iters.checked ], [ %tmp12, %for.body6.preheader ], [ undef, %middle.block ]

30
llvm/test/CodeGen/X86/implicit-null-checks.mir
View File

@@ -5,15 +5,15 @@
target triple = "x86_64-apple-macosx"
;; Positive test
define i32 @imp_null_check_with_bitwise_op_0(ptr %x, i32 %val) {
define i32 @imp_null_check_with_bitwise_op_0(ptr %x, i32 %val, i1 %arg) {
entry:
br i1 undef, label %is_null, label %not_null, !make.implicit !0
br i1 %arg, label %is_null, label %not_null, !make.implicit !0
is_null:
ret i32 42
not_null:
br i1 undef, label %ret_100, label %ret_200
br i1 %arg, label %ret_100, label %ret_200
ret_100:
ret i32 100
@@ -24,15 +24,15 @@
;; Negative test. The regalloc is such that we cannot hoist the
;; instruction materializing 2200000 into $eax
define i32 @imp_null_check_with_bitwise_op_1(ptr %x, i32 %val, ptr %ptr) {
define i32 @imp_null_check_with_bitwise_op_1(ptr %x, i32 %val, ptr %ptr, i1 %arg) {
entry:
br i1 undef, label %is_null, label %not_null, !make.implicit !0
br i1 %arg, label %is_null, label %not_null, !make.implicit !0
is_null:
ret i32 undef
not_null:
br i1 undef, label %ret_100, label %ret_200
br i1 %arg, label %ret_100, label %ret_200
ret_100:
ret i32 100
@@ -43,15 +43,15 @@
;; Negative test: IR is identical to
;; @imp_null_check_with_bitwise_op_0 but MIR differs.
define i32 @imp_null_check_with_bitwise_op_2(ptr %x, i32 %val) {
define i32 @imp_null_check_with_bitwise_op_2(ptr %x, i32 %val, i1 %arg) {
entry:
br i1 undef, label %is_null, label %not_null, !make.implicit !0
br i1 %arg, label %is_null, label %not_null, !make.implicit !0
is_null:
ret i32 42
not_null:
br i1 undef, label %ret_100, label %ret_200
br i1 %arg, label %ret_100, label %ret_200
ret_100:
ret i32 100
@@ -62,15 +62,15 @@
;; Negative test: IR is identical to
;; @imp_null_check_with_bitwise_op_0 but MIR differs.
define i32 @imp_null_check_with_bitwise_op_3(ptr %x, i32 %val) {
define i32 @imp_null_check_with_bitwise_op_3(ptr %x, i32 %val, i1 %arg) {
entry:
br i1 undef, label %is_null, label %not_null, !make.implicit !0
br i1 %arg, label %is_null, label %not_null, !make.implicit !0
is_null:
ret i32 42
not_null:
br i1 undef, label %ret_100, label %ret_200
br i1 %arg, label %ret_100, label %ret_200
ret_100:
ret i32 100
@@ -80,15 +80,15 @@
}
;; Positive test
define i32 @imp_null_check_with_bitwise_op_4(ptr %x, i32 %val) {
define i32 @imp_null_check_with_bitwise_op_4(ptr %x, i32 %val, i1 %arg) {
entry:
br i1 undef, label %is_null, label %not_null, !make.implicit !0
br i1 %arg, label %is_null, label %not_null, !make.implicit !0
is_null:
ret i32 42
not_null:
br i1 undef, label %ret_100, label %ret_200
br i1 %arg, label %ret_100, label %ret_200
ret_100:
ret i32 100

6
llvm/test/CodeGen/X86/interval-update-remat.ll
View File

@@ -17,13 +17,13 @@ target triple = "i386-unknown-linux-gnu"
@f = external global i16, align 2
@.str = external unnamed_addr constant [12 x i8], align 1
define void @fn1() {
define void @fn1(i1 %arg) {
entry:
%tmp = load i64, ptr @b, align 8
%or = or i64 0, 3299921317
%and = and i64 %or, %tmp
%tmp1 = load i32, ptr @d, align 4
br i1 undef, label %lor.rhs, label %lor.end
br i1 %arg, label %lor.rhs, label %lor.end
lor.rhs: ; preds = %entry
%tobool3 = icmp ne i8 undef, 0
@@ -32,7 +32,7 @@ lor.rhs: ; preds = %entry
lor.end: ; preds = %lor.rhs, %entry
%lor.ext = zext i1 undef to i32
%tmp2 = load i64, ptr @e, align 8
br i1 undef, label %lor.rhs5, label %lor.end7
br i1 %arg, label %lor.rhs5, label %lor.end7
lor.rhs5: ; preds = %lor.end
br label %lor.end7

11
llvm/test/CodeGen/X86/jump_sign.ll
View File

@@ -249,16 +249,16 @@ define void @func_o() nounwind uwtable {
; CHECK-NEXT: .LBB12_7: # %if.else.i97
entry:
%0 = load i16, ptr undef, align 2
br i1 undef, label %if.then.i, label %if.end.i
br i1 poison, label %if.then.i, label %if.end.i
if.then.i: ; preds = %entry
unreachable
if.end.i: ; preds = %entry
br i1 undef, label %sw.bb, label %sw.default
br i1 poison, label %sw.bb, label %sw.default
sw.bb: ; preds = %if.end.i
br i1 undef, label %if.then44, label %if.end29
br i1 poison, label %if.then44, label %if.end29
if.end29: ; preds = %sw.bb
%1 = urem i16 %0, 10
@@ -267,7 +267,7 @@ if.end29: ; preds = %sw.bb
br i1 %cmp25, label %if.then44, label %sw.default
sw.default: ; preds = %if.end29, %if.end.i
br i1 undef, label %if.then.i96, label %if.else.i97
br i1 poison, label %if.then.i96, label %if.else.i97
if.then.i96: ; preds = %sw.default
unreachable
@@ -277,7 +277,7 @@ if.else.i97: ; preds = %sw.default
if.then44: ; preds = %if.end29, %sw.bb
%aModeRefSel.1.ph = phi i16 [ %., %if.end29 ], [ 3, %sw.bb ]
br i1 undef, label %if.then.i103, label %if.else.i104
br i1 poison, label %if.then.i103, label %if.else.i104
if.then.i103: ; preds = %if.then44
unreachable
@@ -420,4 +420,3 @@ if.end:
}
!1 = !{!"branch_weights", i32 2, i32 1}

4
llvm/test/CodeGen/X86/loop-strength-reduce-crash.ll
View File

@@ -7,7 +7,7 @@
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.12.0"
define void @foo() {
define void @foo(i1 %arg) {
entry:
br label %for
@@ -17,7 +17,7 @@ for:
store i32 %next, ptr undef, align 4
%add = add i64 %0, 9223372036854775807
%inc = add nsw i32 %next, 1
br i1 undef, label %exit, label %for
br i1 %arg, label %exit, label %for
exit:
store i64 %add, ptr undef

4
llvm/test/CodeGen/X86/lsr-crash-empty-uses.ll
View File

@@ -3,7 +3,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "x86_64-unknown-linux-gnu"
; CHECK-LABEL: @hoge
define void @hoge() {
define void @hoge(i1 %arg) {
bb:
%tmp = sext i32 undef to i64
%tmp3 = sub nsw i64 0, %tmp
@@ -21,7 +21,7 @@ bb7: ; preds = %bb7, %bb4
br i1 true, label %bb11, label %bb7
bb11: ; preds = %bb7
br i1 undef, label %bb20, label %bb12
br i1 %arg, label %bb20, label %bb12
bb12: ; preds = %bb11
br label %bb13

20
llvm/test/CodeGen/X86/lsr-delayed-fold.ll
View File

@@ -30,7 +30,7 @@ bb24: ; preds = %bb21, %bb11
; ScalarEvolution should be able to correctly expand the crazy addrec here.
; PR6914
define void @int323() nounwind {
define void @int323(i1 %arg) nounwind {
entry:
br label %for.cond
@@ -38,7 +38,7 @@ for.cond: ; preds = %lbl_264, %for.inc,
%g_263.tmp.1 = phi i8 [ undef, %entry ], [ %g_263.tmp.1, %for.cond ]
%p_95.addr.0 = phi i8 [ 0, %entry ], [ %add, %for.cond ]
%add = add i8 %p_95.addr.0, 1 ; <i8> [#uses=1]
br i1 undef, label %for.cond, label %lbl_264
br i1 %arg, label %for.cond, label %lbl_264
lbl_264: ; preds = %if.end, %lbl_264.preheader
%g_263.tmp.0 = phi i8 [ %g_263.tmp.1, %for.cond ] ; <i8> [#uses=1]
@@ -56,13 +56,13 @@ lbl_264: ; preds = %if.end, %lbl_264.pr
%struct.Bu = type { i32, i32, i32 }
define void @_Z3fooP2Bui(ptr nocapture %bu) {
define void @_Z3fooP2Bui(ptr nocapture %bu, i1 %arg) {
entry:
br label %for.body
for.body: ; preds = %for.inc131, %entry
%indvar = phi i64 [ %indvar.next, %for.inc131 ], [ 0, %entry ] ; <i64> [#uses=3]
br i1 undef, label %for.inc131, label %lor.lhs.false
br i1 %arg, label %for.inc131, label %lor.lhs.false
lor.lhs.false: ; preds = %for.body
%tmp15 = add i64 %indvar, 1 ; <i64> [#uses=1]
@@ -123,11 +123,11 @@ for.body123: ; preds = %for.body123, %lor.l
%add129 = add i32 %mul, %j.03 ; <i32> [#uses=1]
tail call void undef(i32 %add129)
%inc = add nsw i32 %j.03, 1 ; <i32> [#uses=1]
br i1 undef, label %for.inc131, label %for.body123
br i1 %arg, label %for.inc131, label %for.body123
for.inc131: ; preds = %for.body123, %for.body
%indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1]
br i1 undef, label %for.end134, label %for.body
br i1 %arg, label %for.end134, label %for.body
for.end134: ; preds = %for.inc131
ret void
@@ -138,14 +138,14 @@ for.end134: ; preds = %for.inc131
; require insert point adjustment.
; PR7306
define fastcc i32 @GetOptimum() nounwind {
define fastcc i32 @GetOptimum(i1 %arg) nounwind {
bb:
br label %bb1
bb1: ; preds = %bb1, %bb
%t = phi i32 [ 0, %bb ], [ %t2, %bb1 ] ; <i32> [#uses=1]
%t2 = add i32 %t, undef ; <i32> [#uses=3]
br i1 undef, label %bb1, label %bb3
br i1 %arg, label %bb1, label %bb3
bb3: ; preds = %bb1
%t4 = add i32 undef, -1 ; <i32> [#uses=1]
@@ -155,13 +155,13 @@ bb5: ; preds = %bb16, %bb3
%t6 = phi i32 [ %t17, %bb16 ], [ 0, %bb3 ] ; <i32> [#uses=3]
%t7 = add i32 undef, %t6 ; <i32> [#uses=2]
%t8 = add i32 %t4, %t6 ; <i32> [#uses=1]
br i1 undef, label %bb9, label %bb10
br i1 %arg, label %bb9, label %bb10
bb9: ; preds = %bb5
br label %bb10
bb10: ; preds = %bb9, %bb5
br i1 undef, label %bb11, label %bb16
br i1 %arg, label %bb11, label %bb16
bb11: ; preds = %bb10
%t12 = icmp ugt i32 %t7, %t2 ; <i1> [#uses=1]

4
llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
View File

@@ -52,7 +52,7 @@ define void @PR24199(i32 %a0) {
entry:
%i = alloca %struct.A, align 8
%tobool = icmp ne i32 %a0, 0
br i1 undef, label %if.end, label %if.then
br i1 poison, label %if.end, label %if.then
if.then:
br label %if.end
@@ -96,5 +96,3 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
!4 = !DIExpression()
!5 = !DILocalVariable(name: "this", arg: 1, scope: !3, flags: DIFlagArtificial | DIFlagObjectPointer)
!6 = !DILocation(line: 0, scope: !3)

4
llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll
View File

@@ -21,10 +21,10 @@ define void @testfn(ptr nocapture %p) {
; CHECK-LABEL: testfn_scalar
; CHECK: retq
define void @testfn_scalar(ptr nocapture %j) local_unnamed_addr #0 align 2 {
define void @testfn_scalar(ptr nocapture %j, i1 %arg) local_unnamed_addr #0 align 2 {
entry:
%0 = bitcast i64 undef to <2 x float>
br i1 undef, label %if.end, label %if.then
br i1 %arg, label %if.end, label %if.then
if.then: ; preds = %entry
unreachable

4
llvm/test/CodeGen/X86/misched-crash.ll
View File

@@ -4,7 +4,7 @@ target triple = "x86_64-apple-macosx10"
; This function contains a cmp instruction with two users.
; Hoisting the last use requires trimming the EFLAGS live range to the second.
define void @rdar13353090(ptr %plane, i64 %_x1, i64 %_x2) {
define void @rdar13353090(ptr %plane, i64 %_x1, i64 %_x2, i1 %arg) {
entry:
%cmp = icmp ult i64 %_x1, %_x2
%cond = select i1 %cmp, i64 %_x1, i64 %_x2
@@ -33,7 +33,7 @@ for.body34.i: ; preds = %for.inc39.i, %if.th
for.inc39.i: ; preds = %for.body34.i
%inc41.i = add i64 %index.178.i, 1
br i1 undef, label %return, label %for.body34.i
br i1 %arg, label %return, label %for.body34.i
return: ; preds = %for.inc39.i, %for.body34.i, %land.lhs.true21, %entry
ret void

8
llvm/test/CodeGen/X86/pr10475.ll
View File

@@ -2,19 +2,19 @@
; No check in a crash test
define void @autogen_262380_1000() {
define void @autogen_262380_1000(i1 %arg) {
BB:
br label %CF79
CF79: ; preds = %CF79, %BB
br i1 undef, label %CF79, label %CF84.critedge.critedge
br i1 %arg, label %CF79, label %CF84.critedge.critedge
CF84.critedge.critedge: ; preds = %CF79
%L35 = load <8 x i32>, ptr undef
br label %CF85
CF85: ; preds = %CF85, %CF84.critedge.critedge
br i1 undef, label %CF85, label %CF86
br i1 %arg, label %CF85, label %CF86
CF86: ; preds = %CF86, %CF85
%B61 = sub <8 x i32> %L35, zeroinitializer
@@ -23,7 +23,7 @@ CF86: ; preds = %CF86, %CF85
br i1 %E73, label %CF86, label %CF87
CF87: ; preds = %CF87, %CF86
br i1 undef, label %CF87, label %CF88
br i1 %arg, label %CF87, label %CF88
CF88: ; preds = %CF87
ret void

4
llvm/test/CodeGen/X86/pr11998.ll
View File

@@ -1,13 +1,13 @@
; RUN: llc < %s -mcpu=corei7-avx -mtriple=x86_64-- -mattr=+avx
define void @autogen_51367_5000(i8) {
define void @autogen_51367_5000(i8, i1 %arg) {
BB:
%B = srem i8 55, %0
%B9 = shl i8 %B, %B
br label %CF
CF: ; preds = %CF, %BB
br i1 undef, label %CF, label %CF403
br i1 %arg, label %CF, label %CF403
CF403: ; preds = %CF403, %CF
%S44 = icmp eq i8 %B9, %0

2
llvm/test/CodeGen/X86/pr32108.ll
View File

@@ -13,7 +13,7 @@ BB:
br label %CF243
CF243: ; preds = %CF243, %BB
br i1 undef, label %CF243, label %CF257
br i1 poison, label %CF243, label %CF257
CF257: ; preds = %CF243
%Shuff144 = shufflevector <4 x i1> undef, <4 x i1> %Cmp45, <4 x i32> <i32 undef, i32 undef, i32 5, i32 undef>

2
llvm/test/CodeGen/X86/pr50254.ll
View File

@@ -37,7 +37,7 @@ entry:
br label %for.body
for.body: ; preds = %entry
br i1 undef, label %for.end, label %for.body.1
br i1 poison, label %for.end, label %for.body.1
for.end: ; preds = %for.body
store i16 %xor1, ptr @d.e, align 4

2
llvm/test/CodeGen/X86/pr57673.ll
View File

@@ -100,7 +100,7 @@ bb_entry:
br label %bb_8
bb_8: ; preds = %bb_last, %bb_entry
br i1 undef, label %bb_last, label %bb_mid
br i1 poison, label %bb_last, label %bb_mid
bb_mid: ; preds = %bb_8
%i4 = getelementptr inbounds %t10, ptr %i1, i64 0, i32 1, i64 32

30
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
View File

@@ -331,13 +331,13 @@ if.end:
]
if.then4:
br i1 undef, label %SyTime.exit, label %if.then.i
br i1 poison, label %SyTime.exit, label %if.then.i
if.then.i:
unreachable
SyTime.exit:
br i1 undef, label %SyTime.exit2681, label %if.then.i2673
br i1 poison, label %SyTime.exit2681, label %if.then.i2673
if.then.i2673:
unreachable
@@ -349,7 +349,7 @@ land.lhs.true14:
unreachable
if.end25:
br i1 undef, label %SyTime.exit2720, label %if.then.i2712
br i1 poison, label %SyTime.exit2720, label %if.then.i2712
if.then.i2712:
unreachable
@@ -406,7 +406,7 @@ do.end:
%mul167 = shl i32 %rep.6, 2
%rep.8 = select i1 %cmp164, i32 %mul167, i32 %rep.6
%..ch.19 = select i1 false, i32 2, i32 0
br i1 undef, label %while.body200, label %while.end1465
br i1 poison, label %while.body200, label %while.end1465
while.body200:
%dec3386.in = phi i32 [ %dec3386, %while.cond197.backedge ], [ %rep.8, %do.end ]
@@ -444,7 +444,7 @@ while.cond1037.preheader:
br i1 %cmp10393273, label %if.end1070, label %land.rhs1041
while.cond635.preheader:
br i1 undef, label %for.body643.us, label %while.cond661
br i1 poison, label %for.body643.us, label %while.cond661
for.body643.us:
br label %for.body643.us
@@ -488,7 +488,7 @@ land.rhs485:
br i1 %isascii.i.i27763151, label %cond.true.i.i2780, label %cond.false.i.i2782
cond.true.i.i2780:
br i1 undef, label %land.lhs.true490, label %lor.rhs500
br i1 poison, label %land.lhs.true490, label %lor.rhs500
cond.false.i.i2782:
unreachable
@@ -499,10 +499,10 @@ land.lhs.true490:
lor.rhs500:
; Make sure spill is hoisted to a cold preheader in outside loop.
%call3.i.i2792 = call i32 @__maskrune(i32 undef, i64 256)
br i1 undef, label %land.lhs.true504, label %do.body479.backedge
br i1 poison, label %land.lhs.true504, label %do.body479.backedge
land.lhs.true504:
br i1 undef, label %do.body479.backedge, label %if.end517
br i1 poison, label %do.body479.backedge, label %if.end517
do.body479.backedge:
%incdec.ptr480 = getelementptr i8, ptr %incdec.ptr4803316, i64 1
@@ -531,10 +531,10 @@ for.cond534:
br i1 %cmp536, label %for.cond542.preheader, label %for.cond534
for.cond542.preheader:
br i1 undef, label %for.body545, label %for.end552
br i1 poison, label %for.body545, label %for.end552
for.body545:
br i1 undef, label %for.end552, label %for.body545
br i1 poison, label %for.end552, label %for.body545
for.end552:
%s.2.lcssa = phi ptr [ undef, %for.cond542.preheader ], [ %q.4, %for.body545 ]
@@ -554,7 +554,7 @@ while.cond864:
br label %while.cond864
sw.bb956:
br i1 undef, label %if.then959, label %while.cond197.backedge
br i1 poison, label %if.then959, label %while.cond197.backedge
if.then959:
br label %while.cond962
@@ -600,7 +600,7 @@ while.end1465:
]
for.cond1480.preheader:
br i1 undef, label %for.body1606.lr.ph, label %for.end1609
br i1 poison, label %for.body1606.lr.ph, label %for.end1609
if.then1477:
%p.1.lcssa3539 = phi ptr [ null, %while.end1465 ], [ null, %while.end1465 ], [ null, %while.end1465 ], [ null, %while.end1465 ], [ %line, %while.body200 ]
@@ -614,7 +614,7 @@ for.body1606.lr.ph:
br label %for.end1609
for.end1609:
br i1 undef, label %for.cond1659.preheader, label %land.lhs.true1614
br i1 poison, label %for.cond1659.preheader, label %land.lhs.true1614
land.lhs.true1614:
br label %for.cond1659.preheader
@@ -631,13 +631,13 @@ while.body1703.lr.ph:
unreachable
while.cond1683.preheader:
br i1 undef, label %while.body1691, label %while.end1693
br i1 poison, label %while.body1691, label %while.end1693
while.body1679:
%oldc.43406 = phi i32 [ %inc, %syEchoch.exit3070 ], [ %oldc.1.lcssa, %for.body1664.lr.ph ]
%3 = load ptr, ptr %echo.i3101, align 8, !tbaa !6
%call.i3062 = call i32 @fileno(ptr %3)
br i1 undef, label %if.then.i3069, label %syEchoch.exit3070
br i1 poison, label %if.then.i3069, label %syEchoch.exit3070
if.then.i3069:
br label %syEchoch.exit3070

2
llvm/test/CodeGen/X86/shift-combine.ll
View File

@@ -408,7 +408,7 @@ define dso_local void @PR42880(i32 %t0) {
%x = ptrtoint ptr %add.ptr.i94 to i32
%sub2 = sub i32 %x, 0
%div = sdiv exact i32 %sub2, 24
br i1 undef, label %if, label %then
br i1 poison, label %if, label %then
then:
%t1 = xor i32 %div, -1

3
llvm/test/CodeGen/X86/shuffle-combine-crash.ll
View File

@@ -28,7 +28,7 @@ define void @sample_test() {
; CHECK-NEXT: movd %xmm0, (%rax)
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: retq
br i1 undef, label %5, label %1
br i1 poison, label %5, label %1
; <label>:1 ; preds = %0
%2 = load <4 x i8>, ptr undef
@@ -40,4 +40,3 @@ define void @sample_test() {
; <label>:5 ; preds = %1, %0
ret void
}

8
llvm/test/CodeGen/X86/stackmap.ll
View File

@@ -379,23 +379,23 @@ entry:
; CHECK-NEXT: .short 6
; CHECK-NEXT: .short 0
; CHECK-NEXT: .long
define void @spillSubReg(i64 %arg) #0 {
define void @spillSubReg(i64 %arg, i1 %arg2) #0 {
bb:
br i1 undef, label %bb1, label %bb2
br i1 %arg2, label %bb1, label %bb2
bb1:
unreachable
bb2:
%tmp = load i64, ptr inttoptr (i64 140685446136880 to ptr)
br i1 undef, label %bb16, label %bb17
br i1 %arg2, label %bb16, label %bb17
bb16:
unreachable
bb17:
%tmp32 = trunc i64 %tmp to i32
br i1 undef, label %bb60, label %bb61
br i1 %arg2, label %bb60, label %bb61
bb60:
tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind

2
llvm/test/CodeGen/X86/swifterror.ll
View File

@@ -1014,7 +1014,7 @@ define void @swifterror_isel(ptr) {
; CHECK-i386-NEXT: retl
entry:
%swifterror = alloca swifterror ptr, align 8
br i1 undef, label %5, label %1
br i1 poison, label %5, label %1
%2 = phi i16 [ %4, %1 ], [ undef, %entry ]
%3 = call i1 undef(i16 %2, ptr swiftself %0, ptr nocapture swifterror %swifterror)

2
llvm/test/CodeGen/X86/switch.ll
View File

@@ -2563,7 +2563,7 @@ define i32 @pr27135(i32 %i) {
; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
; NOOPT-NEXT: retq
entry:
br i1 undef, label %sw, label %end
br i1 poison, label %sw, label %end
sw:
switch i32 %i, label %end [
i32 99, label %sw.bb

4
llvm/test/CodeGen/X86/tail-merge-unreachable.ll
View File

@@ -1,8 +1,8 @@
; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -verify-machineinstrs | FileCheck %s
define i32 @tail_merge_unreachable(i32 %i) {
define i32 @tail_merge_unreachable(i32 %i, i1 %arg) {
entry:
br i1 undef, label %sw, label %end
br i1 %arg, label %sw, label %end
sw:
switch i32 %i, label %end [
i32 99, label %sw.bb

4
llvm/test/CodeGen/X86/unreachable-loop-sinking.ll
View File

@@ -7,9 +7,9 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
define double @fn1(ptr %arg, i64 %arg1) {
define double @fn1(ptr %arg, i64 %arg1, i1 %arg2) {
Entry:
br i1 undef, label %Body, label %Exit
br i1 %arg2, label %Body, label %Exit
Exit: ; preds = %Brancher7, %Entry
ret double undef

6
llvm/test/CodeGen/X86/update-terminator.mir
View File

@@ -10,14 +10,14 @@
declare void @dummy3()
; Function Attrs: nounwind
define void @f2() {
br i1 undef, label %bb1, label %bb3
define void @f2(i1 %arg) {
br i1 %arg, label %bb1, label %bb3
bb1:
call void @dummy1()
call void @dummy1()
call void @dummy1()
br i1 undef, label %bb2, label %bb2
br i1 %arg, label %bb2, label %bb2
bb2:
call void @dummy2()

2
llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
View File

@@ -190,7 +190,7 @@ define i64 @PR55050() {
entry:
%i275 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> undef, <16 x i8> zeroinitializer)
%i277 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> undef, <16 x i8> zeroinitializer)
br i1 undef, label %exit, label %if
br i1 poison, label %exit, label %if
if:
%i298 = bitcast <2 x i64> %i275 to <4 x i32>

10
llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
View File

@@ -868,7 +868,7 @@ define void @infiniteloop() {
; DISABLE-NEXT: popq %rbp
; DISABLE-NEXT: retq
entry:
br i1 undef, label %if.then, label %if.end
br i1 poison, label %if.then, label %if.end
if.then:
%ptr = alloca i32, i32 4
@@ -983,7 +983,7 @@ define void @infiniteloop2() {
; DISABLE-NEXT: popq %rbp
; DISABLE-NEXT: retq
entry:
br i1 undef, label %if.then, label %if.end
br i1 poison, label %if.then, label %if.end
if.then:
%ptr = alloca i32, i32 4
@@ -994,7 +994,7 @@ for.body: ; preds = %for.body, %entry
%call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
%add = add nsw i32 %call, %sum.03
store i32 %add, ptr %ptr
br i1 undef, label %body1, label %body2
br i1 poison, label %body1, label %body2
body1:
tail call void asm sideeffect "nop", "~{ebx}"()
@@ -1074,10 +1074,10 @@ define void @infiniteloop3() {
; DISABLE-NEXT: LBB12_7: ## %end
; DISABLE-NEXT: retq
entry:
br i1 undef, label %loop2a, label %body
br i1 poison, label %loop2a, label %body
body: ; preds = %entry
br i1 undef, label %loop2a, label %end
br i1 poison, label %loop2a, label %end
loop1: ; preds = %loop2a, %loop2b
%var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ]