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[AMDGPU][GFX908][DOC][NFC] Update assembler syntax description

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Summary of changes:
- Remove dst for global_atomic_add_f32, global_atomic_pk_add_f16.
- Make vdata input-only for buffer_atomic_add_f32, buffer_atomic_pk_add_f16.
- Other minor improvements.
This commit is contained in:
Dmitry Preobrazhensky
2022-07-01 12:34:59 +03:00
parent 26708fa166
commit 3a4d9b6a68
31 changed files with 145 additions and 197 deletions
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173
llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
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@@ -34,131 +34,128 @@ Instructions
FLAT
-----------------------
----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
global_atomic_add_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst>`::ref:`opt<amdgpu_synid_gfx908_opt>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr>`, :ref:`vdata<amdgpu_synid_gfx908_vdata>`, :ref:`saddr<amdgpu_synid_gfx908_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst>`::ref:`opt<amdgpu_synid_gfx908_opt>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr>`, :ref:`vdata<amdgpu_synid_gfx908_vdata>`, :ref:`saddr<amdgpu_synid_gfx908_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`slc<amdgpu_synid_slc>`
**INSTRUCTION** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
global_atomic_add_f32 :ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx908_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx908_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_pk_add_f16 :ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx908_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx908_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`slc<amdgpu_synid_slc>`
MUBUF
-----------------------
-----
.. parsed-literal::
**INSTRUCTION** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
buffer_atomic_add_f32 :ref:`vdata<amdgpu_synid_gfx908_vdata_1>`::ref:`dst<amdgpu_synid_gfx908_dst>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr_1>`, :ref:`srsrc<amdgpu_synid_gfx908_srsrc>`, :ref:`soffset<amdgpu_synid_gfx908_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_pk_add_f16 :ref:`vdata<amdgpu_synid_gfx908_vdata_1>`::ref:`dst<amdgpu_synid_gfx908_dst>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr_1>`, :ref:`srsrc<amdgpu_synid_gfx908_srsrc>`, :ref:`soffset<amdgpu_synid_gfx908_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`slc<amdgpu_synid_slc>`
**INSTRUCTION** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
buffer_atomic_add_f32 :ref:`vdata<amdgpu_synid_gfx908_vdata_fe1edf>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx908_srsrc>`, :ref:`soffset<amdgpu_synid_gfx908_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_pk_add_f16 :ref:`vdata<amdgpu_synid_gfx908_vdata_fe1edf>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx908_srsrc>`, :ref:`soffset<amdgpu_synid_gfx908_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`slc<amdgpu_synid_slc>`
VOP2
-----------------------
----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`
v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`
v_dot2c_i32_i16_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`
v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`
v_dot8c_i32_i4_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`
v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc>`::ref:`m<amdgpu_synid_gfx908_m>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`::ref:`m<amdgpu_synid_gfx908_m>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`
v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>`
v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_1>`::ref:`m<amdgpu_synid_gfx908_m_1>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`m<amdgpu_synid_gfx908_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`
v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`
v_dot2c_i32_i16_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`
v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`
v_dot8c_i32_i4_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`
v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`
v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`
v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
VOP3
-----------------------
----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`::ref:`m<amdgpu_synid_gfx908_m>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`m<amdgpu_synid_gfx908_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`
v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`
VOP3P
-----------------------
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.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
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v_accvgpr_read_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`vsrc<amdgpu_synid_gfx908_vsrc_1>`
v_accvgpr_write_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_2>`, :ref:`src<amdgpu_synid_gfx908_src_3>`
v_dot2_f32_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot2_i32_i16 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_4>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_5>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`i32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot2_u32_u16 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_4>`::ref:`u16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_5>`::ref:`u16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`u32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot4_i32_i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`i32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot4_u32_u8 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`::ref:`u8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`u8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`u32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot8_i32_i4 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`i32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot8_u32_u4 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`::ref:`u4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`u4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`u32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`::ref:`m<amdgpu_synid_gfx908_m>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`m<amdgpu_synid_gfx908_m>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`m<amdgpu_synid_gfx908_m>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`::ref:`m<amdgpu_synid_gfx908_m>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`m<amdgpu_synid_gfx908_m>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`m<amdgpu_synid_gfx908_m>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_1>`, :ref:`src0<amdgpu_synid_gfx908_src_2>`::ref:`m<amdgpu_synid_gfx908_m>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_1>`::ref:`m<amdgpu_synid_gfx908_m>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_1>`::ref:`m<amdgpu_synid_gfx908_m>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_mfma_f32_16x16x16f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x1f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_4>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_5>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x2bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_4>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_5>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x4f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_4>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_5>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x4f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x8bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x1f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_5>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_6>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x2bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_5>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_6>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x2f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_4>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_5>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x4bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_4>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_5>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x4f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_5>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_6>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x8f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_4>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_5>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_4x4x1f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_4x4x2bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_4x4x4f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_2>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_3>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_16x16x16i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_3>`::ref:`i32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_3>`::ref:`i32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_16x16x4i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_4>`::ref:`i32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_5>`::ref:`i32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_32x32x4i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_5>`::ref:`i32x32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_6>`::ref:`i32x32<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_32x32x8i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_4>`::ref:`i32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_5>`::ref:`i32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_4x4x4i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_3>`::ref:`i32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_3>`::ref:`i32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_accvgpr_read_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx908_vsrc_1027ca>`
v_accvgpr_write_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_78dd0a>`, :ref:`src<amdgpu_synid_gfx908_src_58d119>`
v_dot2_f32_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot2_i32_i16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_955b45>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d95796>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`i32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot2_u32_u16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_955b45>`::ref:`u16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d95796>`::ref:`u16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`u32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot4_i32_i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`i32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot4_u32_u8 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`u8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`u32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot8_i32_i4 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`i32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot8_u32_u4 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`u4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`u4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`u32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_mfma_f32_16x16x16f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_bcee7a>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_f3d248>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x1f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x2bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x4f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x4f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_bcee7a>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_f3d248>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x8bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_bcee7a>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_f3d248>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x1f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_2c8d1e>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_036abe>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x2bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_2c8d1e>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_036abe>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x2f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x4bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x4f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_2c8d1e>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_036abe>`::ref:`f32x32<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_32x32x8f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_4x4x1f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_bcee7a>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_f3d248>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_4x4x2bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_bcee7a>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_f3d248>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_4x4x4f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_bcee7a>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_f3d248>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_16x16x16i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_bcee7a>`::ref:`i32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_f3d248>`::ref:`i32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_16x16x4i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`i32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`i32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_32x32x4i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_2c8d1e>`::ref:`i32x32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_036abe>`::ref:`i32x32<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_32x32x8i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`i32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`i32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_i32_4x4x4i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_bcee7a>`::ref:`i32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_f3d248>`::ref:`i32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
.. |---| unicode:: U+02014 .. em dash
.. toctree::
:hidden:
gfx908_dst
gfx908_fx_operand
gfx908_m
gfx908_m_1
gfx908_opt
gfx908_m_254bcb
gfx908_m_f5d306
gfx908_saddr
gfx908_soffset
gfx908_src
gfx908_src_1
gfx908_src_2
gfx908_src_3
gfx908_src_4
gfx908_src_5
gfx908_src_4e78e6
gfx908_src_58d119
gfx908_src_73ab34
gfx908_src_955b45
gfx908_src_d578c4
gfx908_src_d95796
gfx908_srsrc
gfx908_type_deviation
gfx908_vaddr
gfx908_vaddr_1
gfx908_vdata
gfx908_vdata_1
gfx908_vdst
gfx908_vdst_1
gfx908_vdst_2
gfx908_vdst_3
gfx908_vdst_4
gfx908_vdst_5
gfx908_vsrc
gfx908_vsrc_1
gfx908_vsrc_2
gfx908_vsrc_3
gfx908_vsrc_4
gfx908_vsrc_5
gfx908_vsrc_6
gfx908_vaddr_0212e3
gfx908_vaddr_b73dc0
gfx908_vdata_6802ce
gfx908_vdata_fe1edf
gfx908_vdst_0c4ef8
gfx908_vdst_2c8d1e
gfx908_vdst_78dd0a
gfx908_vdst_89680f
gfx908_vdst_bcee7a
gfx908_vsrc_036abe
gfx908_vsrc_1027ca
gfx908_vsrc_2d4632
gfx908_vsrc_6802ce
gfx908_vsrc_9ad749
gfx908_vsrc_be4895
gfx908_vsrc_f3d248

13
llvm/docs/AMDGPU/gfx908_dst.rst
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@@ -1,13 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx908_dst:
dst
===
This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.

2
llvm/docs/AMDGPU/gfx908_m_1.rst → llvm/docs/AMDGPU/gfx908_m_254bcb.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_m_1:
.. _amdgpu_synid_gfx908_m_254bcb:
m
=

2
llvm/docs/AMDGPU/gfx908_m.rst → llvm/docs/AMDGPU/gfx908_m_f5d306.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_m:
.. _amdgpu_synid_gfx908_m_f5d306:
m
=

13
llvm/docs/AMDGPU/gfx908_opt.rst
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@@ -1,13 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx908_opt:
opt
===
This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.

2
llvm/docs/AMDGPU/gfx908_saddr.rst
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@@ -12,7 +12,7 @@ saddr
An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
See :ref:`vaddr<amdgpu_synid_gfx908_vaddr>` for description of available addressing modes.
See :ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>` for description of available addressing modes.
*Size:* 2 dwords.

2
llvm/docs/AMDGPU/gfx908_src_2.rst → llvm/docs/AMDGPU/gfx908_src_4e78e6.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_src_2:
.. _amdgpu_synid_gfx908_src_4e78e6:
src
===

2
llvm/docs/AMDGPU/gfx908_src_3.rst → llvm/docs/AMDGPU/gfx908_src_58d119.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_src_3:
.. _amdgpu_synid_gfx908_src_58d119:
src
===

2
llvm/docs/AMDGPU/gfx908_src.rst → llvm/docs/AMDGPU/gfx908_src_73ab34.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_src:
.. _amdgpu_synid_gfx908_src_73ab34:
src
===

2
llvm/docs/AMDGPU/gfx908_src_4.rst → llvm/docs/AMDGPU/gfx908_src_955b45.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_src_4:
.. _amdgpu_synid_gfx908_src_955b45:
src
===

2
llvm/docs/AMDGPU/gfx908_src_1.rst → llvm/docs/AMDGPU/gfx908_src_d578c4.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_src_1:
.. _amdgpu_synid_gfx908_src_d578c4:
src
===

2
llvm/docs/AMDGPU/gfx908_src_5.rst → llvm/docs/AMDGPU/gfx908_src_d95796.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_src_5:
.. _amdgpu_synid_gfx908_src_d95796:
src
===

20
llvm/docs/AMDGPU/gfx908_vaddr.rst
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@@ -1,20 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx908_vaddr:
vaddr
=====
A 64-bit flat global address or a 32-bit offset depending on addressing mode:
* Address = :ref:`vaddr<amdgpu_synid_gfx908_vaddr>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx908_vaddr>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx908_saddr>` set to :ref:`off<amdgpu_synid_off>`.
* Address = :ref:`saddr<amdgpu_synid_gfx908_saddr>` + :ref:`vaddr<amdgpu_synid_gfx908_vaddr>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx908_vaddr>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx908_saddr>` is not :ref:`off<amdgpu_synid_off>`.
*Size:* 1 or 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

20
llvm/docs/AMDGPU/gfx908_vaddr_0212e3.rst Normal file
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@@ -0,0 +1,20 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx908_vaddr_0212e3:
vaddr
=====
A 64-bit flat global address or a 32-bit offset depending on addressing mode:
* Address = :ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx908_saddr>` set to :ref:`off<amdgpu_synid_off>`.
* Address = :ref:`saddr<amdgpu_synid_gfx908_saddr>` + :ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx908_saddr>` is not :ref:`off<amdgpu_synid_off>`.
*Size:* 1 or 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

2
llvm/docs/AMDGPU/gfx908_vaddr_1.rst → llvm/docs/AMDGPU/gfx908_vaddr_b73dc0.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vaddr_1:
.. _amdgpu_synid_gfx908_vaddr_b73dc0:
vaddr
=====

21
llvm/docs/AMDGPU/gfx908_vdata_1.rst
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@@ -1,21 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx908_vdata_1:
vdata
=====
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

2
llvm/docs/AMDGPU/gfx908_vdata.rst → llvm/docs/AMDGPU/gfx908_vdata_6802ce.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vdata:
.. _amdgpu_synid_gfx908_vdata_6802ce:
vdata
=====

17
llvm/docs/AMDGPU/gfx908_vdata_fe1edf.rst Normal file
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@@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx908_vdata_fe1edf:
vdata
=====
Input data for an atomic instruction.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

19
llvm/docs/AMDGPU/gfx908_vdst.rst
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@@ -1,19 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx908_vdst:
vdst
====
Data returned by a 32-bit atomic flat instruction.
This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

2
llvm/docs/AMDGPU/gfx908_vdst_4.rst → llvm/docs/AMDGPU/gfx908_vdst_0c4ef8.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vdst_4:
.. _amdgpu_synid_gfx908_vdst_0c4ef8:
vdst
====

2
llvm/docs/AMDGPU/gfx908_vdst_5.rst → llvm/docs/AMDGPU/gfx908_vdst_2c8d1e.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vdst_5:
.. _amdgpu_synid_gfx908_vdst_2c8d1e:
vdst
====

2
llvm/docs/AMDGPU/gfx908_vdst_2.rst → llvm/docs/AMDGPU/gfx908_vdst_78dd0a.rst
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@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vdst_2:
.. _amdgpu_synid_gfx908_vdst_78dd0a:
vdst
====

2
llvm/docs/AMDGPU/gfx908_vdst_1.rst → llvm/docs/AMDGPU/gfx908_vdst_89680f.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vdst_1:
.. _amdgpu_synid_gfx908_vdst_89680f:
vdst
====

2
llvm/docs/AMDGPU/gfx908_vdst_3.rst → llvm/docs/AMDGPU/gfx908_vdst_bcee7a.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vdst_3:
.. _amdgpu_synid_gfx908_vdst_bcee7a:
vdst
====

2
llvm/docs/AMDGPU/gfx908_vsrc_6.rst → llvm/docs/AMDGPU/gfx908_vsrc_036abe.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vsrc_6:
.. _amdgpu_synid_gfx908_vsrc_036abe:
vsrc
====

2
llvm/docs/AMDGPU/gfx908_vsrc_1.rst → llvm/docs/AMDGPU/gfx908_vsrc_1027ca.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vsrc_1:
.. _amdgpu_synid_gfx908_vsrc_1027ca:
vsrc
====

2
llvm/docs/AMDGPU/gfx908_vsrc_5.rst → llvm/docs/AMDGPU/gfx908_vsrc_2d4632.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vsrc_5:
.. _amdgpu_synid_gfx908_vsrc_2d4632:
vsrc
====

2
llvm/docs/AMDGPU/gfx908_vsrc.rst → llvm/docs/AMDGPU/gfx908_vsrc_6802ce.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vsrc:
.. _amdgpu_synid_gfx908_vsrc_6802ce:
vsrc
====

2
llvm/docs/AMDGPU/gfx908_vsrc_2.rst → llvm/docs/AMDGPU/gfx908_vsrc_9ad749.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vsrc_2:
.. _amdgpu_synid_gfx908_vsrc_9ad749:
vsrc
====

2
llvm/docs/AMDGPU/gfx908_vsrc_4.rst → llvm/docs/AMDGPU/gfx908_vsrc_be4895.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vsrc_4:
.. _amdgpu_synid_gfx908_vsrc_be4895:
vsrc
====

2
llvm/docs/AMDGPU/gfx908_vsrc_3.rst → llvm/docs/AMDGPU/gfx908_vsrc_f3d248.rst
View File

@@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx908_vsrc_3:
.. _amdgpu_synid_gfx908_vsrc_f3d248:
vsrc
====