[SystemZ] Optimize vector zero/sign extensions
Generate more efficient code for zero or sign extensions where the source is a subvector generated via SHUFFLE_VECTOR. Specifically, recognize patterns corresponding to (series of) VECTOR UNPACK instructions, or the VECTOR SIGN EXTEND TO DOUBLEWORD instruction. As a special case, also handle zero or sign extensions of a vector element to i128. Fixes: https://github.com/llvm/llvm-project/issues/129576 Fixes: https://github.com/llvm/llvm-project/issues/129899
This commit is contained in:
Ulrich Weigand
@@ -5800,7 +5800,8 @@ static SDValue getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
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namespace {
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// Describes a general N-operand vector shuffle.
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struct GeneralShuffle {
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GeneralShuffle(EVT vt) : VT(vt), UnpackFromEltSize(UINT_MAX) {}
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GeneralShuffle(EVT vt)
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: VT(vt), UnpackFromEltSize(UINT_MAX), UnpackLow(false) {}
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void addUndef();
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bool add(SDValue, unsigned);
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SDValue getNode(SelectionDAG &, const SDLoc &);
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@@ -5821,8 +5822,10 @@ struct GeneralShuffle {
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// Holds a value of 1, 2 or 4 if a final unpack has been prepared for.
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unsigned UnpackFromEltSize;
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// True if the final unpack uses the low half.
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bool UnpackLow;
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};
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}
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} // namespace
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// Add an extra undefined element to the shuffle.
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void GeneralShuffle::addUndef() {
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@@ -6027,11 +6030,21 @@ void GeneralShuffle::tryPrepareForUnpack() {
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if (MatchUnpack) {
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if (Ops.size() == 2) {
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// Don't use unpack if a single source operand needs rearrangement.
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for (unsigned i = 0; i < SystemZ::VectorBytes / 2; i++)
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if (SrcBytes[i] != -1 && SrcBytes[i] % 16 != int(i)) {
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bool CanUseUnpackLow = true, CanUseUnpackHigh = true;
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for (unsigned i = 0; i < SystemZ::VectorBytes / 2; i++) {
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if (SrcBytes[i] == -1)
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continue;
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if (SrcBytes[i] % 16 != int(i))
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CanUseUnpackHigh = false;
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if (SrcBytes[i] % 16 != int(i + SystemZ::VectorBytes / 2))
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CanUseUnpackLow = false;
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if (!CanUseUnpackLow && !CanUseUnpackHigh) {
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UnpackFromEltSize = UINT_MAX;
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return;
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}
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}
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if (!CanUseUnpackHigh)
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UnpackLow = true;
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}
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break;
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}
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@@ -6046,13 +6059,19 @@ void GeneralShuffle::tryPrepareForUnpack() {
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// Apply the unpack in reverse to the Bytes array.
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unsigned B = 0;
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if (UnpackLow) {
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while (B < SystemZ::VectorBytes / 2)
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Bytes[B++] = -1;
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}
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for (unsigned Elt = 0; Elt < SystemZ::VectorBytes;) {
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Elt += UnpackFromEltSize;
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for (unsigned i = 0; i < UnpackFromEltSize; i++, Elt++, B++)
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Bytes[B] = Bytes[Elt];
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}
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while (B < SystemZ::VectorBytes)
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Bytes[B++] = -1;
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if (!UnpackLow) {
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while (B < SystemZ::VectorBytes)
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Bytes[B++] = -1;
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}
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// Remove the zero vector from Ops
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Ops.erase(&Ops[ZeroVecOpNo]);
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@@ -6079,7 +6098,9 @@ SDValue GeneralShuffle::insertUnpackIfPrepared(SelectionDAG &DAG,
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unsigned OutBits = InBits * 2;
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EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits),
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SystemZ::VectorBits / OutBits);
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return DAG.getNode(SystemZISD::UNPACKL_HIGH, DL, OutVT, PackedOp);
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return DAG.getNode(UnpackLow ? SystemZISD::UNPACKL_LOW
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: SystemZISD::UNPACKL_HIGH,
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DL, OutVT, PackedOp);
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}
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// Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
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@@ -6486,12 +6507,55 @@ lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const {
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EVT InVT = PackedOp.getValueType();
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unsigned ToBits = OutVT.getScalarSizeInBits();
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unsigned FromBits = InVT.getScalarSizeInBits();
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unsigned StartOffset = 0;
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// If the input is a VECTOR_SHUFFLE, there are a number of important
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// cases where we can directly implement the sign-extension of the
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// original input lanes of the shuffle.
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if (PackedOp.getOpcode() == ISD::VECTOR_SHUFFLE) {
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ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(PackedOp.getNode());
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ArrayRef<int> ShuffleMask = SVN->getMask();
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int OutNumElts = OutVT.getVectorNumElements();
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// Recognize the special case where the sign-extension can be done
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// by the VSEG instruction. Handled via the default expander.
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if (ToBits == 64 && OutNumElts == 2) {
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int NumElem = ToBits / FromBits;
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if (ShuffleMask[0] == NumElem - 1 && ShuffleMask[1] == 2 * NumElem - 1)
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return SDValue();
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}
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// Recognize the special case where we can fold the shuffle by
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// replacing some of the UNPACK_HIGH with UNPACK_LOW.
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int StartOffsetCandidate = -1;
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for (int Elt = 0; Elt < OutNumElts; Elt++) {
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if (ShuffleMask[Elt] == -1)
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continue;
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if (ShuffleMask[Elt] % OutNumElts == Elt) {
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if (StartOffsetCandidate == -1)
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StartOffsetCandidate = ShuffleMask[Elt] - Elt;
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if (StartOffsetCandidate == ShuffleMask[Elt] - Elt)
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continue;
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}
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StartOffsetCandidate = -1;
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break;
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}
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if (StartOffsetCandidate != -1) {
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StartOffset = StartOffsetCandidate;
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PackedOp = PackedOp.getOperand(0);
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}
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}
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do {
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FromBits *= 2;
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EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits),
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SystemZ::VectorBits / FromBits);
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PackedOp =
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DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(PackedOp), OutVT, PackedOp);
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unsigned OutNumElts = SystemZ::VectorBits / FromBits;
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EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits), OutNumElts);
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unsigned Opcode = SystemZISD::UNPACK_HIGH;
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if (StartOffset >= OutNumElts) {
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Opcode = SystemZISD::UNPACK_LOW;
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StartOffset -= OutNumElts;
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}
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PackedOp = DAG.getNode(Opcode, SDLoc(PackedOp), OutVT, PackedOp);
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} while (FromBits != ToBits);
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return PackedOp;
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}
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@@ -1970,6 +1970,22 @@ let Predicates = [FeatureVector] in {
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(VLEG (VGBM 0), bdxaddr12only:$addr, 1)>;
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}
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// Zero-extensions from VR element to i128 on arch15.
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let Predicates = [FeatureVectorEnhancements3] in {
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def : Pat<(i128 (zext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),
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(VUPLHG VR128:$src)>;
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def : Pat<(i128 (zext (i64 (z_vector_extract (v2i64 VR128:$src), 1)))),
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(VUPLLG VR128:$src)>;
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def : Pat<(i128 (zext (i32 (z_vector_extract (v4i32 VR128:$src), 0)))),
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(VUPLHG (VUPLHF VR128:$src))>;
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def : Pat<(i128 (zext (i32 (z_vector_extract (v4i32 VR128:$src), 1)))),
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(VUPLHG (VUPLLF VR128:$src))>;
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def : Pat<(i128 (zext (i32 (z_vector_extract (v4i32 VR128:$src), 2)))),
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(VUPLLG (VUPLHF VR128:$src))>;
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def : Pat<(i128 (zext (i32 (z_vector_extract (v4i32 VR128:$src), 3)))),
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(VUPLLG (VUPLLF VR128:$src))>;
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}
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// In-register i128 sign-extensions on arch15.
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let Predicates = [FeatureVectorEnhancements3] in {
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def : Pat<(i128 (sext_inreg VR128:$x, i8)), (VUPLG (VSEGB VR128:$x))>;
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@@ -2034,6 +2050,22 @@ let Predicates = [FeatureVector] in {
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(VSRAB (VLREPG bdxaddr12only:$addr), (VREPIB 64))>;
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}
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// Sign-extensions from VR element to i128 on arch15.
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let Predicates = [FeatureVectorEnhancements3] in {
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def : Pat<(i128 (sext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),
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(VUPHG VR128:$src)>;
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def : Pat<(i128 (sext (i64 (z_vector_extract (v2i64 VR128:$src), 1)))),
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(VUPLG VR128:$src)>;
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def : Pat<(i128 (sext (i32 (z_vector_extract (v4i32 VR128:$src), 0)))),
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(VUPHG (VUPHF VR128:$src))>;
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def : Pat<(i128 (sext (i32 (z_vector_extract (v4i32 VR128:$src), 1)))),
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(VUPHG (VUPLF VR128:$src))>;
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def : Pat<(i128 (sext (i32 (z_vector_extract (v4i32 VR128:$src), 2)))),
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(VUPLG (VUPHF VR128:$src))>;
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def : Pat<(i128 (sext (i32 (z_vector_extract (v4i32 VR128:$src), 3)))),
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(VUPLG (VUPLF VR128:$src))>;
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}
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// i128 comparison pseudo-instructions.
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let Predicates = [FeatureVector], Defs = [CC],
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usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
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@@ -58,8 +58,7 @@ define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16
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; CHECK: # %bb.0:
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; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v26
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; CHECK-DAG: vuphb [[REG2:%v[0-9]+]], [[REG0]]
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; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
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; CHECK-DAG: vuphb [[REG1]], [[REG1]]
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; CHECK-DAG: vuplb [[REG1:%v[0-9]+]], [[REG0]]
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; CHECK-DAG: vceqh [[REG3:%v[0-9]+]], %v28, %v25
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; CHECK-DAG: vceqh [[REG4:%v[0-9]+]], %v30, %v27
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; CHECK-DAG: vl [[REG5:%v[0-9]+]], 176(%r15)
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@@ -186,10 +185,9 @@ define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x
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; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v28, %v30
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; CHECK-NEXT: vx [[REG2:%v[0-9]+]], [[REG0]], [[REG1]]
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; CHECK-DAG: vuphh [[REG3:%v[0-9]+]], [[REG2]]
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; CHECK-DAG: vmrlg [[REG4:%v[0-9]+]], [[REG2]], [[REG2]]
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; CHECK-DAG: vuphh [[REG5:%v[0-9]+]], [[REG4]]
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; CHECK-DAG: vuplhw [[REG4:%v[0-9]+]], [[REG2]]
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; CHECK-NEXT: vsel %v24, %v25, %v29, [[REG3]]
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; CHECK-NEXT: vsel %v26, %v27, %v31, [[REG5]]
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; CHECK-NEXT: vsel %v26, %v27, %v31, [[REG4]]
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; CHECK-NEXT: br %r14
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%cmp0 = icmp eq <8 x i16> %val1, %val2
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%cmp1 = icmp eq <8 x i16> %val3, %val4
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@@ -347,10 +345,9 @@ define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
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; CHECK-NEXT: vuphh %v1, %v1
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; CHECK-NEXT: vn %v0, %v0, %v1
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; CHECK-DAG: vuphf [[REG0:%v[0-9]+]], %v0
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; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], %v0, %v0
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; CHECK-DAG: vuphf [[REG2:%v[0-9]+]], [[REG1]]
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; CHECK-DAG: vuplf [[REG1:%v[0-9]+]], %v0
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; CHECK-NEXT: vsel %v24, %v25, %v29, [[REG0]]
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; CHECK-NEXT: vsel %v26, %v27, %v31, [[REG2]]
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; CHECK-NEXT: vsel %v26, %v27, %v31, [[REG1]]
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; CHECK-NEXT: br %r14
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%cmp0 = icmp eq <4 x i32> %val1, %val2
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%cmp1 = icmp eq <4 x i16> %val3, %val4
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@@ -455,14 +452,13 @@ define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x
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; CHECK-LABEL: fun24:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vceqf [[REG0:%v[0-9]+]], %v25, %v27
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; CHECK-NEXT: vuphf [[REG1:%v[0-9]+]], [[REG0]]
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; CHECK-NEXT: vmrlg [[REG2:%v[0-9]+]], [[REG0]], [[REG0]]
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; CHECK-DAG: vuphf [[REG1:%v[0-9]+]], [[REG0]]
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; CHECK-DAG: vuplf [[REG2:%v[0-9]+]], [[REG0]]
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; CHECK-DAG: vceqg [[REG3:%v[0-9]+]], %v24, %v28
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; CHECK-DAG: vceqg [[REG4:%v[0-9]+]], %v26, %v30
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; CHECK-DAG: vuphf [[REG5:%v[0-9]+]], [[REG2]]
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; CHECK-DAG: vl [[REG6:%v[0-9]+]], 176(%r15)
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; CHECK-DAG: vl [[REG7:%v[0-9]+]], 160(%r15)
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; CHECK-DAG: vx [[REG8:%v[0-9]+]], [[REG4]], [[REG5]]
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; CHECK-DAG: vx [[REG8:%v[0-9]+]], [[REG4]], [[REG2]]
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; CHECK-DAG: vx [[REG9:%v[0-9]+]], [[REG3]], [[REG1]]
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; CHECK-DAG: vsel %v24, %v29, [[REG7]], [[REG9]]
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; CHECK-DAG: vsel %v26, %v31, [[REG6]], [[REG8]]
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@@ -631,8 +627,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %va
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; CHECK-NEXT: vfchdb %v2, %v3, %v2
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; CHECK-NEXT: vpkg %v1, %v2, %v1
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; CHECK-NEXT: vx %v0, %v0, %v1
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; CHECK-NEXT: vmrlg %v1, %v0, %v0
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; CHECK-NEXT: vuphf %v1, %v1
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; CHECK-NEXT: vuplf %v1, %v0
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; CHECK-NEXT: vuphf %v0, %v0
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; CHECK-NEXT: vsel %v24, %v25, %v29, %v0
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; CHECK-NEXT: vsel %v26, %v27, %v31, %v1
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@@ -643,8 +638,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %va
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; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
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; CHECK-Z14-NEXT: vfchsb %v1, %v28, %v30
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; CHECK-Z14-NEXT: vx %v0, %v0, %v1
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; CHECK-Z14-NEXT: vmrlg %v1, %v0, %v0
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; CHECK-Z14-NEXT: vuphf %v1, %v1
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; CHECK-Z14-NEXT: vuplf %v1, %v0
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; CHECK-Z14-NEXT: vuphf %v0, %v0
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; CHECK-Z14-NEXT: vsel %v24, %v25, %v29, %v0
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; CHECK-Z14-NEXT: vsel %v26, %v27, %v31, %v1
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@@ -816,11 +810,10 @@ define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %
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; CHECK-DAG: vfchdb [[REG11:%v[0-9]+]], [[REG9]], [[REG7]]
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; CHECK-DAG: vpkg [[REG12:%v[0-9]+]], [[REG11]], [[REG4]]
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; CHECK-DAG: vuphf [[REG13:%v[0-9]+]], [[REG12]]
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; CHECK-DAG: vmrlg [[REG14:%v[0-9]+]], [[REG12]], [[REG12]]
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; CHECK-NEXT: vfchdb [[REG15:%v[0-9]+]], %v24, %v28
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; CHECK-NEXT: vfchdb [[REG16:%v[0-9]+]], %v26, %v30
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; CHECK-NEXT: vuphf [[REG17:%v[0-9]+]], [[REG14]]
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; CHECK-NEXT: vn [[REG18:%v[0-9]+]], [[REG16]], [[REG17]]
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; CHECK-DAG: vuplf [[REG14:%v[0-9]+]], [[REG12]]
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; CHECK-DAG: vfchdb [[REG15:%v[0-9]+]], %v24, %v28
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; CHECK-DAG: vfchdb [[REG16:%v[0-9]+]], %v26, %v30
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; CHECK-NEXT: vn [[REG18:%v[0-9]+]], [[REG16]], [[REG14]]
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; CHECK-NEXT: vn [[REG19:%v[0-9]+]], [[REG15]], [[REG13]]
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; CHECK-NEXT: vsel %v24, %v29, [[REG10]], [[REG19]]
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; CHECK-NEXT: vsel %v26, %v31, [[REG8]], [[REG18]]
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@@ -829,13 +822,12 @@ define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %
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; CHECK-Z14-LABEL: fun34:
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; CHECK-Z14: # %bb.0:
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; CHECK-Z14-NEXT: vfchsb %v4, %v25, %v27
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; CHECK-Z14-NEXT: vl %v0, 176(%r15)
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; CHECK-Z14-NEXT: vl %v1, 160(%r15)
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; CHECK-Z14-NEXT: vfchdb %v2, %v24, %v28
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; CHECK-Z14-NEXT: vfchdb %v3, %v26, %v30
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; CHECK-Z14-NEXT: vuphf %v5, %v4
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; CHECK-Z14-NEXT: vmrlg %v4, %v4, %v4
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; CHECK-Z14-DAG: vfchdb %v2, %v24, %v28
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; CHECK-Z14-DAG: vfchdb %v3, %v26, %v30
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; CHECK-Z14-DAG: vuphf %v4, %v4
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; CHECK-Z14-DAG: vl %v0, 176(%r15)
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; CHECK-Z14-DAG: vl %v1, 160(%r15)
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; CHECK-Z14-NEXT: vuplf %v4, %v4
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; CHECK-Z14-NEXT: vn %v3, %v3, %v4
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; CHECK-Z14-NEXT: vn %v2, %v2, %v5
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; CHECK-Z14-NEXT: vsel %v24, %v29, %v1, %v2
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@@ -43,8 +43,7 @@ define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16
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; CHECK: # %bb.0:
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; CHECK-NEXT: vceqb %v0, %v24, %v26
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; CHECK-DAG: vuphb [[REG0:%v[0-9]+]], %v0
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; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], %v0, %v0
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; CHECK-DAG: vuphb [[REG1]], [[REG1]]
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; CHECK-DAG: vuplb [[REG1:%v[0-9]+]], %v0
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; CHECK-NEXT: vsel %v24, %v28, %v25, [[REG0]]
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; CHECK-NEXT: vsel %v26, %v30, %v27, [[REG1]]
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; CHECK-NEXT: br %r14
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@@ -129,8 +128,7 @@ define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x
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; CHECK: # %bb.0:
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; CHECK-NEXT: vceqh %v0, %v24, %v26
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||||
; CHECK-DAG: vuphh [[REG0:%v[0-9]+]], %v0
|
||||
; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], %v0, %v0
|
||||
; CHECK-DAG: vuphh [[REG1]], [[REG1]]
|
||||
; CHECK-DAG: vuplhw [[REG1:%v[0-9]+]], %v0
|
||||
; CHECK-NEXT: vsel %v24, %v28, %v25, [[REG0]]
|
||||
; CHECK-NEXT: vsel %v26, %v30, %v27, [[REG1]]
|
||||
; CHECK-NEXT: br %r14
|
||||
@@ -228,8 +226,7 @@ define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vceqf %v0, %v24, %v26
|
||||
; CHECK-DAG: vuphf [[REG0:%v[0-9]+]], %v0
|
||||
; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], %v0, %v0
|
||||
; CHECK-DAG: vuphf [[REG1]], [[REG1]]
|
||||
; CHECK-DAG: vuplf [[REG1]], %v0
|
||||
; CHECK-NEXT: vsel %v24, %v28, %v25, [[REG0]]
|
||||
; CHECK-NEXT: vsel %v26, %v30, %v27, [[REG1]]
|
||||
; CHECK-NEXT: br %r14
|
||||
@@ -428,8 +425,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x double> %v
|
||||
; CHECK-NEXT: vldeb %v2, %v2
|
||||
; CHECK-NEXT: vfchdb %v1, %v2, %v1
|
||||
; CHECK-NEXT: vpkg [[REG0:%v[0-9]+]], %v1, %v0
|
||||
; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
|
||||
; CHECK-DAG: vuphf [[REG1]], [[REG1]]
|
||||
; CHECK-DAG: vuplf [[REG1:%v[0-9]+]], [[REG0]]
|
||||
; CHECK-DAG: vuphf [[REG2:%v[0-9]+]], [[REG0]]
|
||||
; CHECK-NEXT: vsel %v24, %v28, %v25, [[REG2]]
|
||||
; CHECK-NEXT: vsel %v26, %v30, %v27, [[REG1]]
|
||||
@@ -439,8 +435,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x double> %v
|
||||
; CHECK-Z14: # %bb.0:
|
||||
; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
|
||||
; CHECK-Z14-DAG: vuphf [[REG0:%v[0-9]+]], %v0
|
||||
; CHECK-Z14-DAG: vmrlg [[REG1:%v[0-9]+]], %v0, %v0
|
||||
; CHECK-Z14-DAG: vuphf [[REG1]], [[REG1]]
|
||||
; CHECK-Z14-DAG: vuplf [[REG1:%v[0-9]+]], %v0
|
||||
; CHECK-Z14-NEXT: vsel %v24, %v28, %v25, [[REG0]]
|
||||
; CHECK-Z14-NEXT: vsel %v26, %v30, %v27, [[REG1]]
|
||||
; CHECK-Z14-NEXT: br %r14
|
||||
|
||||
@@ -143,19 +143,17 @@ define void @fun8(<2 x i64> %dwords, ptr %ptr) {
|
||||
; Test that this results in vectorized conversions.
|
||||
define void @fun9(ptr %Src, ptr %ptr) {
|
||||
; CHECK-LABEL: fun9
|
||||
; Z15: larl %r1, .LCPI9_0
|
||||
; Z15-NEXT: vl %v0, 16(%r2), 4
|
||||
; Z15: vl %v0, 16(%r2), 4
|
||||
; Z15-NEXT: vl %v1, 0(%r2), 4
|
||||
; Z15-NEXT: vl %v2, 0(%r1), 3
|
||||
; Z15-NEXT: vperm %v2, %v2, %v1, %v2
|
||||
; Z15-NEXT: vuplhh %v1, %v1
|
||||
; Z15-NEXT: vuplhh %v2, %v1
|
||||
; Z15-NEXT: vupllh %v1, %v1
|
||||
; Z15-NEXT: vuplhh %v0, %v0
|
||||
; Z15-NEXT: vcelfb %v2, %v2, 0, 0
|
||||
; Z15-NEXT: vcelfb %v1, %v1, 0, 0
|
||||
; Z15-NEXT: vcelfb %v0, %v0, 0, 0
|
||||
; Z15-NEXT: vsteg %v0, 32(%r3), 0
|
||||
; Z15-NEXT: vst %v2, 16(%r3), 4
|
||||
; Z15-NEXT: vst %v1, 0(%r3), 4
|
||||
; Z15-NEXT: vst %v1, 16(%r3), 4
|
||||
; Z15-NEXT: vst %v2, 0(%r3), 4
|
||||
; Z15-NEXT: br %r14
|
||||
|
||||
%Val = load <10 x i16>, ptr %Src
|
||||
|
||||
@@ -180,3 +180,33 @@ define <2 x i64> @f16(<16 x i32> %val) {
|
||||
%vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1
|
||||
ret <2 x i64> %vec1
|
||||
}
|
||||
|
||||
; Test a shufflevector-based v2i8->v2i64 extension.
|
||||
define <2 x i64> @f17(<16 x i8> %val) {
|
||||
; CHECK-LABEL: f17:
|
||||
; CHECK: vsegb %v24, %v24
|
||||
; CHECK: br %r14
|
||||
%shuf = shufflevector <16 x i8> %val, <16 x i8> poison, <2 x i32> <i32 7, i32 15>
|
||||
%ret = sext <2 x i8> %shuf to <2 x i64>
|
||||
ret <2 x i64> %ret
|
||||
}
|
||||
|
||||
; Test a shufflevector-based v2i16->v2i64 extension.
|
||||
define <2 x i64> @f18(<8 x i16> %val) {
|
||||
; CHECK-LABEL: f18:
|
||||
; CHECK: vsegh %v24, %v24
|
||||
; CHECK: br %r14
|
||||
%shuf = shufflevector <8 x i16> %val, <8 x i16> poison, <2 x i32> <i32 3, i32 7>
|
||||
%ret = sext <2 x i16> %shuf to <2 x i64>
|
||||
ret <2 x i64> %ret
|
||||
}
|
||||
|
||||
; Test a shufflevector-based v2i32->v2i64 extension.
|
||||
define <2 x i64> @f19(<4 x i32> %val) {
|
||||
; CHECK-LABEL: f19:
|
||||
; CHECK: vsegf %v24, %v24
|
||||
; CHECK: br %r14
|
||||
%shuf = shufflevector <4 x i32> %val, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
|
||||
%ret = sext <2 x i32> %shuf to <2 x i64>
|
||||
ret <2 x i64> %ret
|
||||
}
|
||||
|
||||
270
llvm/test/CodeGen/SystemZ/vec-unpack-01.ll
Normal file
270
llvm/test/CodeGen/SystemZ/vec-unpack-01.ll
Normal file
@@ -0,0 +1,270 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
|
||||
|
||||
define <8 x i16> @f1(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphb %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%1 = sext <8 x i8> %0 to <8 x i16>
|
||||
ret <8 x i16> %1
|
||||
}
|
||||
|
||||
define <8 x i16> @f2(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplb %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
%1 = sext <8 x i8> %0 to <8 x i16>
|
||||
ret <8 x i16> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @f3(<8 x i16> %a) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphh %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%1 = sext <4 x i16> %0 to <4 x i32>
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @f4(<8 x i16> %a) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplhw %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
%1 = sext <4 x i16> %0 to <4 x i32>
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @f5(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphb %v0, %v24
|
||||
; CHECK-NEXT: vuphh %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%1 = sext <4 x i8> %0 to <4 x i32>
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @f6(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphb %v0, %v24
|
||||
; CHECK-NEXT: vuplhw %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
%1 = sext <4 x i8> %0 to <4 x i32>
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @f7(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f7:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplb %v0, %v24
|
||||
; CHECK-NEXT: vuphh %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
%1 = sext <4 x i8> %0 to <4 x i32>
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @f8(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f8:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplb %v0, %v24
|
||||
; CHECK-NEXT: vuplhw %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
|
||||
%1 = sext <4 x i8> %0 to <4 x i32>
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f9(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f9:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphf %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
|
||||
%1 = sext <2 x i32> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f10(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f10:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplf %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
|
||||
%1 = sext <2 x i32> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f11(<8 x i16> %a) {
|
||||
; CHECK-LABEL: f11:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphh %v0, %v24
|
||||
; CHECK-NEXT: vuphf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 0, i32 1>
|
||||
%1 = sext <2 x i16> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f12(<8 x i16> %a) {
|
||||
; CHECK-LABEL: f12:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphh %v0, %v24
|
||||
; CHECK-NEXT: vuplf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 2, i32 3>
|
||||
%1 = sext <2 x i16> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f13(<8 x i16> %a) {
|
||||
; CHECK-LABEL: f13:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplhw %v0, %v24
|
||||
; CHECK-NEXT: vuphf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 4, i32 5>
|
||||
%1 = sext <2 x i16> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f14(<8 x i16> %a) {
|
||||
; CHECK-LABEL: f14:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplhw %v0, %v24
|
||||
; CHECK-NEXT: vuplf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 6, i32 7>
|
||||
%1 = sext <2 x i16> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f15(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f15:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphb %v0, %v24
|
||||
; CHECK-NEXT: vuphh %v0, %v0
|
||||
; CHECK-NEXT: vuphf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 0, i32 1>
|
||||
%1 = sext <2 x i8> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f16(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f16:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphb %v0, %v24
|
||||
; CHECK-NEXT: vuphh %v0, %v0
|
||||
; CHECK-NEXT: vuplf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 2, i32 3>
|
||||
%1 = sext <2 x i8> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f17(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f17:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphb %v0, %v24
|
||||
; CHECK-NEXT: vuplhw %v0, %v0
|
||||
; CHECK-NEXT: vuphf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 4, i32 5>
|
||||
%1 = sext <2 x i8> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f18(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f18:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphb %v0, %v24
|
||||
; CHECK-NEXT: vuplhw %v0, %v0
|
||||
; CHECK-NEXT: vuplf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 6, i32 7>
|
||||
%1 = sext <2 x i8> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f19(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f19:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplb %v0, %v24
|
||||
; CHECK-NEXT: vuphh %v0, %v0
|
||||
; CHECK-NEXT: vuphf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 8, i32 9>
|
||||
%1 = sext <2 x i8> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f20(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f20:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplb %v0, %v24
|
||||
; CHECK-NEXT: vuphh %v0, %v0
|
||||
; CHECK-NEXT: vuplf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 10, i32 11>
|
||||
%1 = sext <2 x i8> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f21(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f21:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplb %v0, %v24
|
||||
; CHECK-NEXT: vuplhw %v0, %v0
|
||||
; CHECK-NEXT: vuphf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 12, i32 13>
|
||||
%1 = sext <2 x i8> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f22(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f22:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplb %v0, %v24
|
||||
; CHECK-NEXT: vuplhw %v0, %v0
|
||||
; CHECK-NEXT: vuplf %v24, %v0
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 14, i32 15>
|
||||
%1 = sext <2 x i8> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
79
llvm/test/CodeGen/SystemZ/vec-unpack-02.ll
Normal file
79
llvm/test/CodeGen/SystemZ/vec-unpack-02.ll
Normal file
@@ -0,0 +1,79 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
|
||||
|
||||
define i128 @f1(<2 x i64> %a) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphg %v0, %v24
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <2 x i64> %a, i32 0
|
||||
%1 = sext i64 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f2(<2 x i64> %a) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplg %v0, %v24
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <2 x i64> %a, i32 1
|
||||
%1 = sext i64 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f3(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphf %v0, %v24
|
||||
; CHECK-NEXT: vuphg %v0, %v0
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <4 x i32> %a, i32 0
|
||||
%1 = sext i32 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f4(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplf %v0, %v24
|
||||
; CHECK-NEXT: vuphg %v0, %v0
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <4 x i32> %a, i32 1
|
||||
%1 = sext i32 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f5(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuphf %v0, %v24
|
||||
; CHECK-NEXT: vuplg %v0, %v0
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <4 x i32> %a, i32 2
|
||||
%1 = sext i32 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f6(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplf %v0, %v24
|
||||
; CHECK-NEXT: vuplg %v0, %v0
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <4 x i32> %a, i32 3
|
||||
%1 = sext i32 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
70
llvm/test/CodeGen/SystemZ/vec-unpack-03.ll
Normal file
70
llvm/test/CodeGen/SystemZ/vec-unpack-03.ll
Normal file
@@ -0,0 +1,70 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
|
||||
|
||||
define <8 x i16> @f1(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplhb %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%1 = zext <8 x i8> %0 to <8 x i16>
|
||||
ret <8 x i16> %1
|
||||
}
|
||||
|
||||
define <8 x i16> @f2(<16 x i8> %a) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vupllb %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
%1 = zext <8 x i8> %0 to <8 x i16>
|
||||
ret <8 x i16> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @f3(<8 x i16> %a) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplhh %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%1 = zext <4 x i16> %0 to <4 x i32>
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @f4(<8 x i16> %a) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vupllh %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
%1 = zext <4 x i16> %0 to <4 x i32>
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f5(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplhf %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
|
||||
%1 = zext <2 x i32> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
define <2 x i64> @f6(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vupllf %v24, %v24
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
|
||||
%1 = zext <2 x i32> %0 to <2 x i64>
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
79
llvm/test/CodeGen/SystemZ/vec-unpack-04.ll
Normal file
79
llvm/test/CodeGen/SystemZ/vec-unpack-04.ll
Normal file
@@ -0,0 +1,79 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
|
||||
|
||||
define i128 @f1(<2 x i64> %a) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplhg %v0, %v24
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <2 x i64> %a, i32 0
|
||||
%1 = zext i64 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f2(<2 x i64> %a) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vupllg %v0, %v24
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <2 x i64> %a, i32 1
|
||||
%1 = zext i64 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f3(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplhf %v0, %v24
|
||||
; CHECK-NEXT: vuplhg %v0, %v0
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <4 x i32> %a, i32 0
|
||||
%1 = zext i32 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f4(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vupllf %v0, %v24
|
||||
; CHECK-NEXT: vuplhg %v0, %v0
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <4 x i32> %a, i32 1
|
||||
%1 = zext i32 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f5(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vuplhf %v0, %v24
|
||||
; CHECK-NEXT: vupllg %v0, %v0
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <4 x i32> %a, i32 2
|
||||
%1 = zext i32 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @f6(<4 x i32> %a) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: # %bb.0: # %start
|
||||
; CHECK-NEXT: vupllf %v0, %v24
|
||||
; CHECK-NEXT: vupllg %v0, %v0
|
||||
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
||||
; CHECK-NEXT: br %r14
|
||||
start:
|
||||
%0 = extractelement <4 x i32> %a, i32 3
|
||||
%1 = zext i32 %0 to i128
|
||||
ret i128 %1
|
||||
}
|
||||
Reference in New Issue
Block a user