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[CIR][LLVMLowering] Upstream Bitcast lowering (#140774)

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This change adds support for lowering BitCastOp
This commit is contained in:
Amr Hesham
2025-05-21 18:46:57 +02:00
committed by GitHub
parent 9db6c32524
commit 584616c878
2 changed files with 25 additions and 4 deletions
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12
clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
View File

@@ -530,10 +530,18 @@ mlir::LogicalResult CIRToLLVMCastOpLowering::matchAndRewrite(
llvmSrcVal);
return mlir::success();
}
case cir::CastKind::bitcast:
case cir::CastKind::bitcast: {
mlir::Type dstTy = castOp.getType();
mlir::Type llvmDstTy = getTypeConverter()->convertType(dstTy);
assert(!MissingFeatures::cxxABI());
assert(!MissingFeatures::dataMemberType());
break;
mlir::Value llvmSrcVal = adaptor.getOperands().front();
rewriter.replaceOpWithNewOp<mlir::LLVM::BitcastOp>(castOp, llvmDstTy,
llvmSrcVal);
return mlir::success();
}
case cir::CastKind::ptr_to_bool: {
mlir::Value llvmSrcVal = adaptor.getOperands().front();
mlir::Value zeroPtr = rewriter.create<mlir::LLVM::ZeroOp>(

17
clang/test/CIR/CodeGen/cast.cpp
View File

@@ -25,7 +25,6 @@ unsigned char cxxstaticcast_0(unsigned int x) {
// LLVM: %[[R:[0-9]+]] = load i8, ptr %[[RV]], align 1
// LLVM: ret i8 %[[R]]
int cStyleCasts_0(unsigned x1, int x2, float x3, short x4, double x5) {
// CIR: cir.func @_Z13cStyleCasts_0jifsd
// LLVM: define i32 @_Z13cStyleCasts_0jifsd
@@ -103,10 +102,24 @@ void should_not_cast() {
bool x2;
bool ib = (bool)x2; // identity
(void) ib; // void cast
}
// CIR: cir.func @_Z15should_not_castv
// CIR-NOT: cir.cast
// CIR: cir.return
typedef int vi4 __attribute__((vector_size(16)));
typedef double vd2 __attribute__((vector_size(16)));
void bitcast() {
vd2 a = {};
vi4 b = (vi4)a;
}
// CIR: %[[D_VEC:.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double>
// CIR: %[[I_VEC:.*]] = cir.cast(bitcast, %[[D_VEC]] : !cir.vector<2 x !cir.double>), !cir.vector<4 x !s32i>
// LLVM: %[[D_VEC:.*]] = load <2 x double>, ptr {{.*}}, align 16
// LLVM: %[[I_VEC:.*]] = bitcast <2 x double> %[[D_VEC]] to <4 x i32>