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[LLVM][AArch64] Relax SVE/SME codegen predicates for crypto and bitperm instructions. (#145696)

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Adds sve-sha3 to reference FEAT_SVE_SHA3 without specifically enabling
SVE2. The SVE2 requirement for AES, SHA3 and Bitperm is replaced with
SVE for non-streaming function.
This commit is contained in:
Paul Walker
2025-06-26 13:01:07 +01:00
committed by GitHub
parent 3287c1c176
commit 635acfbfca
37 changed files with 131 additions and 101 deletions
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2
clang/test/CodeGen/AArch64/fmv-dependencies.c
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@@ -188,7 +188,7 @@ int caller() {
// CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
// CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-aes,+sve2,+sve2-aes,+v8a"
// CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-bitperm,+sve2,+sve2-bitperm,+v8a"
// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve2,+sve2-sha3,+v8a"
// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve-sha3,+sve2,+sve2-sha3,+v8a"
// CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sm4,+sve,+sve2,+sve2-sm4,+v8a"
// CHECK: attributes #[[wfxt]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt"
// CHECK: attributes #[[cssc]] = { {{.*}} "target-features"="+cssc,+fp-armv8,+neon,+outline-atomics,+v8a"

4
clang/test/Driver/aarch64-implied-sve-features.c
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@@ -46,13 +46,13 @@
// SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "-sve-aes" "-target-feature" "+sve2" "-target-feature" "-sve2-aes"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3+nosve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3-REVERT
// SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3"
// SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "-sve-sha3" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4+nosve2-sm4 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SM4-REVERT
// SVE2-SM4-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sm4"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3
// SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3"
// SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve-sha3" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-AES
// SVE-AES: "-target-feature" "+aes"{{.*}} "-target-feature" "+sve-aes"

2
clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c
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@@ -70,7 +70,7 @@
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension

2
clang/test/Driver/print-enabled-extensions/aarch64-grace.c
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@@ -54,7 +54,7 @@
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension

2
clang/test/Driver/print-enabled-extensions/aarch64-olympus.c
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@@ -70,7 +70,7 @@
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension

3
clang/test/Driver/print-supported-extensions-aarch64.c
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@@ -92,10 +92,11 @@
// CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE Enable Armv9.6-A SVE BFloat16 scaling instructions
// CHECK-NEXT: sve-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply
// CHECK-NEXT: sve-sha3 FEAT_SVE_SHA3 Enable SVE SHA3 instructions
// CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
// CHECK-NEXT: sve2-aes Shorthand for +sve2+sve-aes
// CHECK-NEXT: sve2-bitperm Shorthand for +sve2+sve-bitperm
// CHECK-NEXT: sve2-sha3 FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
// CHECK-NEXT: sve2-sha3 Shorthand for +sve2+sve-sha3
// CHECK-NEXT: sve2-sm4 FEAT_SVE_SM4 Enable SM4 SVE2 instructions
// CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
// CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions

6
llvm/lib/Target/AArch64/AArch64.td
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@@ -63,7 +63,7 @@ def SVE2p1Unsupported : AArch64Unsupported;
def SVE2Unsupported : AArch64Unsupported {
let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
HasSMEF8F32, HasSVEAES, HasSVE2SHA3, HasSVE2SM4, HasSVEBitPerm,
HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVE2SM4, HasSVEBitPerm,
HasSVEB16B16],
SVE2p1Unsupported.F);
}
@@ -80,14 +80,14 @@ def SME2p2Unsupported : AArch64Unsupported;
def SME2p1Unsupported : AArch64Unsupported {
let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1,
HasSME_MOP4, HasSME_TMOP, HasNonStreamingSVE_or_SSVE_FEXPA,
HasNonStreamingSVE2_or_SSVE_BitPerm],
HasNonStreamingSVE_or_SSVE_BitPerm],
SME2p2Unsupported.F);
}
def SME2Unsupported : AArch64Unsupported {
let F = !listconcat([HasSME2, HasSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16,
HasNonStreamingSVE2_or_SSVE_AES],
HasNonStreamingSVE_or_SSVE_AES],
SME2p1Unsupported.F);
}

7
llvm/lib/Target/AArch64/AArch64Features.td
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@@ -373,8 +373,11 @@ def FeatureAliasSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4",
"Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
def FeatureSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3", "FEAT_SVE_SHA3",
"Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
def FeatureSVESHA3 : ExtensionWithMArch<"sve-sha3", "SVESHA3", "FEAT_SVE_SHA3",
"Enable SVE SHA3 instructions", [FeatureSHA3]>;
def FeatureAliasSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3",
"", "Shorthand for +sve2+sve-sha3", [FeatureSVE2, FeatureSVESHA3]>;
def FeatureSVEBitPerm : ExtensionWithMArch<"sve-bitperm", "SVEBitPerm",
"FEAT_SVE_BitPerm", "Enable bit permutation SVE2 instructions">;

29
llvm/lib/Target/AArch64/AArch64InstrInfo.td
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@@ -153,8 +153,8 @@ def HasSVEAES : Predicate<"Subtarget->hasSVEAES()">,
AssemblerPredicateWithAll<(all_of FeatureSVEAES), "sve-aes">;
def HasSVE2SM4 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2SM4()">,
AssemblerPredicateWithAll<(all_of FeatureSVE2SM4), "sve2-sm4">;
def HasSVE2SHA3 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2SHA3()">,
AssemblerPredicateWithAll<(all_of FeatureSVE2SHA3), "sve2-sha3">;
def HasSVESHA3 : Predicate<"Subtarget->hasSVESHA3()">,
AssemblerPredicateWithAll<(all_of FeatureSVESHA3), "sve-sha3">;
def HasSVEBitPerm : Predicate<"Subtarget->hasSVEBitPerm()">,
AssemblerPredicateWithAll<(all_of FeatureSVEBitPerm), "sve-bitperm">;
def HasSMEandIsNonStreamingSafe
@@ -248,11 +248,26 @@ def HasSVE_or_SME
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable()">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),
"sve or sme">;
def HasNonStreamingSVE_or_SME2p1
: Predicate<"Subtarget->isSVEAvailable() ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p1())">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p1),
"sve or sme2p1">;
def HasNonStreamingSVE_or_SME2p2
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2),
"sve or sme2p2">;
def HasNonStreamingSVE_or_SSVE_AES
: Predicate<"Subtarget->isSVEAvailable() ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_AES),
"sve or ssve-aes">;
def HasNonStreamingSVE_or_SSVE_BitPerm
: Predicate<"Subtarget->isSVEAvailable() ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm())">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_BitPerm),
"sve or ssve-bitperm">;
def HasNonStreamingSVE_or_SSVE_FEXPA
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA())">,
@@ -267,11 +282,6 @@ def HasSVE2_or_SME2
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME2),
"sve2 or sme2">;
def HasNonStreamingSVE2_or_SSVE_AES
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_AES),
"sve2 or ssve-aes">;
def HasSVE2p1_or_SME
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
@@ -300,11 +310,6 @@ def HasSMEF16F16_or_SMEF8F16
: Predicate<"Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16())">,
AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16),
"sme-f16f16 or sme-f8f16">;
def HasNonStreamingSVE2_or_SSVE_BitPerm
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_BitPerm),
"sve2 or ssve-bitperm">;
// A subset of NEON instructions are legal in Streaming SVE execution mode,
// so don't need the additional check for 'isNeonAvailable'.

6
llvm/lib/Target/AArch64/AArch64Processors.td
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@@ -897,7 +897,7 @@ def ProcessorFeatures {
FeatureFPAC, FeatureFP16FML, FeatureRandGen,
FeatureSSBS, FeatureLS64, FeatureCLRBHB,
FeatureSPECRES2, FeatureSVEAES, FeatureSVE2SM4,
FeatureSVE2SHA3, FeatureSVE2, FeatureSVEBitPerm, FeatureETE,
FeatureSVESHA3, FeatureSVE2, FeatureSVEBitPerm, FeatureETE,
FeatureMEC, FeatureFAMINMAX, FeatureFP8DOT2, FeatureFP8DOT4,
FeatureFP8FMA, FeatureLUT];
list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeatureAES,
@@ -910,7 +910,7 @@ def ProcessorFeatures {
FeatureLS64, FeatureLUT, FeatureMEC,
FeatureMTE, FeaturePerfMon, FeatureRandGen,
FeatureSPE, FeatureSPE_EEF, FeatureSSBS,
FeatureSVEBitPerm, FeatureSVE2SHA3,
FeatureSVEBitPerm, FeatureSVESHA3,
FeatureSVE2SM4, FeatureSVEAES];
list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON,FeaturePerfMon];
@@ -1107,7 +1107,7 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
FeatureSSBS, FeatureCCIDX,
FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVE2SHA3]);
list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVESHA3]);
// ETE and TRBE are future architecture extensions. We temporarily enable them
// by default for users targeting generic AArch64. The extensions do not

10
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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@@ -4091,7 +4091,7 @@ let Predicates = [HasSVE2_or_SME] in {
defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw", "int_aarch64_sve_whilerw">;
} // End HasSVE2_or_SME
let Predicates = [HasSVEAES, HasNonStreamingSVE2_or_SSVE_AES] in {
let Predicates = [HasSVEAES, HasNonStreamingSVE_or_SSVE_AES] in {
// SVE2 crypto destructive binary operations
let isCommutable = 1 in {
def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8, int_aarch64_sve_aese, nxv16i8>;
@@ -4116,19 +4116,19 @@ let Predicates = [HasSVE2SM4] in {
def SM4E_ZZZ_S : sve2_crypto_des_bin_op<0b10, "sm4e", ZPR32, int_aarch64_sve_sm4e, nxv4i32>;
} // End HasSVE2SM4
let Predicates = [HasSVE2SHA3] in {
let Predicates = [HasSVESHA3, HasNonStreamingSVE_or_SME2p1] in {
// SVE2 crypto constructive binary operations
defm RAX1_ZZZ_D : sve2_crypto_cons_bin_op<0b1, "rax1", ZPR64, int_aarch64_sve_rax1, nxv2i64>;
} // End HasSVE2SHA3
} // End HasSVESHA3, HasNonStreamingSVE_or_SME2p1
let Predicates = [HasSVEBitPerm, HasNonStreamingSVE2_or_SSVE_BitPerm] in {
let Predicates = [HasSVEBitPerm, HasNonStreamingSVE_or_SSVE_BitPerm] in {
// SVE2 bitwise permute
defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext", int_aarch64_sve_bext_x>;
defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep", int_aarch64_sve_bdep_x>;
defm BGRP_ZZZ : sve2_misc_bitwise<0b1110, "bgrp", int_aarch64_sve_bgrp_x>;
}
let Predicates = [HasSVEAES2, HasNonStreamingSVE2_or_SSVE_AES] in {
let Predicates = [HasSVEAES2, HasNonStreamingSVE_or_SSVE_AES] in {
// SVE_AES2 multi-vector instructions (x2)
def AESE_2ZZI_B : sve_crypto_binary_multi2<0b000, "aese">;
def AESD_2ZZI_B : sve_crypto_binary_multi2<0b010, "aesd">;

3
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@@ -3742,7 +3742,8 @@ static const struct Extension {
{"sve-aes", {AArch64::FeatureSVEAES}},
{"sve2-aes", {AArch64::FeatureAliasSVE2AES, AArch64::FeatureSVEAES}},
{"sve2-sm4", {AArch64::FeatureSVE2SM4}},
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"sve-sha3", {AArch64::FeatureSVESHA3}},
{"sve2-sha3", {AArch64::FeatureAliasSVE2SHA3, AArch64::FeatureSVESHA3}},
{"sve-bitperm", {AArch64::FeatureSVEBitPerm}},
{"sve2-bitperm",
{AArch64::FeatureAliasSVE2BitPerm, AArch64::FeatureSVEBitPerm,

7
llvm/lib/TargetParser/AArch64TargetParser.cpp
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@@ -298,6 +298,13 @@ void AArch64::ExtensionSet::disable(ArchExtKind E) {
if (E == AEK_SVE2AES)
disable(AEK_SVEAES);
// sve2-sha3 was historically associated with both FEAT_SVE2 and
// FEAT_SVE_SHA3, the latter is now associated with sve-sha3 and sve2-sha3 has
// become shorthand for +sve2+sve-sha3. For backwards compatibility, when we
// disable sve2-sha3 we must also disable sve-sha3.
if (E == AEK_SVE2SHA3)
disable(AEK_SVESHA3);
if (E == AEK_SVE2BITPERM){
disable(AEK_SVEBITPERM);
disable(AEK_SVE2);

5
llvm/test/CodeGen/AArch64/sve2-intrinsics-bit-permutation.ll
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@@ -1,5 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2,+sve2-bitperm < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-bitperm < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sve-bitperm < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+ssve-bitperm < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+ssve-bitperm -force-streaming < %s | FileCheck %s
;
; BDEP

4
llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
View File

@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-aes < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2,+sve-aes < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sve-aes < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+ssve-aes < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+ssve-aes -force-streaming < %s | FileCheck %s
;
; AESD

2
llvm/test/CodeGen/AArch64/sve2-intrinsics-rax1.ll
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@@ -1,5 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-sha3 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sve-sha3 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1,+sve-sha3 -force-streaming < %s | FileCheck %s
;
; RAX1

2
llvm/test/MC/AArch64/SME2p1/directive-arch_extension-negative.s
View File

@@ -23,5 +23,5 @@ bfadd za.h[w8, 3], {z20.h-z21.h}
.arch_extension ssve-aes
.arch_extension nossve-aes
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
// CHECK: error: instruction requires: sve2 or ssve-aes
// CHECK: error: instruction requires: sve or ssve-aes
// CHECK: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]

2
llvm/test/MC/AArch64/SVE2/aesd.s
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@@ -17,5 +17,5 @@
aesd z0.b, z0.b, z31.b
// CHECK-INST: aesd z0.b, z0.b, z31.b
// CHECK-ENCODING: [0xe0,0xe7,0x22,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes
// CHECK-UNKNOWN: 4522e7e0 <unknown>

2
llvm/test/MC/AArch64/SVE2/aese.s
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@@ -17,5 +17,5 @@
aese z0.b, z0.b, z31.b
// CHECK-INST: aese z0.b, z0.b, z31.b
// CHECK-ENCODING: [0xe0,0xe3,0x22,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes
// CHECK-UNKNOWN: 4522e3e0 <unknown>

4
llvm/test/MC/AArch64/SVE2/aesimc.s
View File

@@ -17,11 +17,11 @@
aesimc z0.b, z0.b
// CHECK-INST: aesimc z0.b, z0.b
// CHECK-ENCODING: [0x00,0xe4,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes
// CHECK-UNKNOWN: 4520e400 <unknown>
aesimc z31.b, z31.b
// CHECK-INST: aesimc z31.b, z31.b
// CHECK-ENCODING: [0x1f,0xe4,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes
// CHECK-UNKNOWN: 4520e41f <unknown>

4
llvm/test/MC/AArch64/SVE2/aesmc.s
View File

@@ -17,11 +17,11 @@
aesmc z0.b, z0.b
// CHECK-INST: aesmc z0.b, z0.b
// CHECK-ENCODING: [0x00,0xe0,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes
// CHECK-UNKNOWN: 4520e000 <unknown>
aesmc z31.b, z31.b
// CHECK-INST: aesmc z31.b, z31.b
// CHECK-ENCODING: [0x1f,0xe0,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes
// CHECK-UNKNOWN: 4520e01f <unknown>

8
llvm/test/MC/AArch64/SVE2/bdep.s
View File

@@ -14,23 +14,23 @@
bdep z0.b, z1.b, z31.b
// CHECK-INST: bdep z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xb4,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 451fb420 <unknown>
bdep z0.h, z1.h, z31.h
// CHECK-INST: bdep z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xb4,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 455fb420 <unknown>
bdep z0.s, z1.s, z31.s
// CHECK-INST: bdep z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xb4,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 459fb420 <unknown>
bdep z0.d, z1.d, z31.d
// CHECK-INST: bdep z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xb4,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 45dfb420 <unknown>

8
llvm/test/MC/AArch64/SVE2/bext.s
View File

@@ -14,23 +14,23 @@
bext z0.b, z1.b, z31.b
// CHECK-INST: bext z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xb0,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 451fb020 <unknown>
bext z0.h, z1.h, z31.h
// CHECK-INST: bext z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xb0,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 455fb020 <unknown>
bext z0.s, z1.s, z31.s
// CHECK-INST: bext z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xb0,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 459fb020 <unknown>
bext z0.d, z1.d, z31.d
// CHECK-INST: bext z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xb0,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 45dfb020 <unknown>

8
llvm/test/MC/AArch64/SVE2/bgrp.s
View File

@@ -14,23 +14,23 @@
bgrp z0.b, z1.b, z31.b
// CHECK-INST: bgrp z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xb8,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 451fb820 <unknown>
bgrp z0.h, z1.h, z31.h
// CHECK-INST: bgrp z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xb8,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 455fb820 <unknown>
bgrp z0.s, z1.s, z31.s
// CHECK-INST: bgrp z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xb8,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 459fb820 <unknown>
bgrp z0.d, z1.d, z31.d
// CHECK-INST: bgrp z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xb8,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-ERROR: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-UNKNOWN: 45dfb820 <unknown>

2
llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
View File

@@ -26,7 +26,7 @@ sm4e z0.s, z0.s, z0.s
.arch armv9-a+sve2-sha3
.arch armv9-a+nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK: error: instruction requires: sve-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
.arch armv9-a+ssve-bitperm

12
llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
View File

@@ -9,7 +9,7 @@ tbx z0.b, z1.b, z2.b
.arch_extension sve-aes
.arch_extension nosve-aes
aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2 or ssve-aes sve-aes
// CHECK: error: instruction requires: sve-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
// nosve2-aes should disable sve-aes but not sve2.
@@ -28,19 +28,13 @@ sm4e z0.s, z0.s, z0.s
.arch_extension sve2-sha3
.arch_extension nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK: error: instruction requires: sve-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
.arch_extension sve2-bitperm
.arch_extension nosve2-bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
.arch_extension sve2-bitperm
.arch_extension nosve2
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: sve2 or ssve-bitperm
// CHECK: error: instruction requires: sve-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
.arch_extension f8f16mm

6
llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
View File

@@ -14,7 +14,7 @@ aesd z23.b, z23.b, z13.b
.cpu generic+sve-aes+nosve-aes
aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2 or ssve-aes sve-aes
// CHECK: error: instruction requires: sve or ssve-aes sve-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
.cpu generic+sve2-sm4
@@ -26,7 +26,7 @@ sm4e z0.s, z0.s, z0.s
.cpu generic+sve2-sha3
.cpu generic+nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK: error: instruction requires: sve or sme2p1 sve-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
.cpu generic+sve2+sve-bitperm
@@ -38,7 +38,7 @@ bgrp z21.s, z10.s, z21.s
.cpu generic+ssve-bitperm
.cpu generic+nossve-bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: sve2 or ssve-bitperm sve-bitperm
// CHECK: error: instruction requires: sve or ssve-bitperm sve-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
.cpu generic+sve2+f8f16mm

2
llvm/test/MC/AArch64/SVE2/pmullb-128.s
View File

@@ -17,5 +17,5 @@
pmullb z29.q, z30.d, z31.d
// CHECK-INST: pmullb z29.q, z30.d, z31.d
// CHECK-ENCODING: [0xdd,0x6b,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes
// CHECK-UNKNOWN: 451f6bdd <unknown>

2
llvm/test/MC/AArch64/SVE2/pmullt-128.s
View File

@@ -17,5 +17,5 @@
pmullt z29.q, z30.d, z31.d
// CHECK-INST: pmullt z29.q, z30.d, z31.d
// CHECK-ENCODING: [0xdd,0x6f,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes
// CHECK-UNKNOWN: 451f6fdd <unknown>

6
llvm/test/MC/AArch64/SVE2/rax1.s
View File

@@ -1,5 +1,9 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sha3 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-sha3 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sve-sha3 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
@@ -13,5 +17,5 @@
rax1 z0.d, z1.d, z31.d
// CHECK-INST: rax1 z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xf4,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2-sha3
// CHECK-ERROR: instruction requires: sve or sme2p1 sve-sha3
// CHECK-UNKNOWN: 453ff420 <unknown>

12
llvm/test/MC/AArch64/SVE2p1/aesd.s
View File

@@ -18,36 +18,36 @@
aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0] // 01000101-00100010-11101100-00000000
// CHECK-INST: aesd { z0.b, z1.b }, { z0.b, z1.b }, z0.q[0]
// CHECK-ENCODING: [0x00,0xec,0x22,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4522ec00 <unknown>
aesd {z20.b-z21.b}, {z20.b-z21.b}, z10.q[2] // 01000101-00110010-11101101-01010100
// CHECK-INST: aesd { z20.b, z21.b }, { z20.b, z21.b }, z10.q[2]
// CHECK-ENCODING: [0x54,0xed,0x32,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4532ed54 <unknown>
aesd {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3] // 01000101-00111010-11101111-11111110
// CHECK-INST: aesd { z30.b, z31.b }, { z30.b, z31.b }, z31.q[3]
// CHECK-ENCODING: [0xfe,0xef,0x3a,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453aeffe <unknown>
// x4
aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0] // 01000101-00100110-11101100-00000000
// CHECK-INST: aesd { z0.b - z3.b }, { z0.b - z3.b }, z0.q[0]
// CHECK-ENCODING: [0x00,0xec,0x26,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4526ec00 <unknown>
aesd {z20.b-z23.b}, {z20.b-z23.b}, z13.q[1] // 01000101-00101110-11101101-10110100
// CHECK-INST: aesd { z20.b - z23.b }, { z20.b - z23.b }, z13.q[1]
// CHECK-ENCODING: [0xb4,0xed,0x2e,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 452eedb4 <unknown>
aesd {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3] // 01000101-00111110-11101111-11111100
// CHECK-INST: aesd { z28.b - z31.b }, { z28.b - z31.b }, z31.q[3]
// CHECK-ENCODING: [0xfc,0xef,0x3e,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453eeffc <unknown>

12
llvm/test/MC/AArch64/SVE2p1/aesdimc.s
View File

@@ -19,36 +19,36 @@
aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0] // 01000101-00100011-11101100-00000000
// CHECK-INST: aesdimc { z0.b, z1.b }, { z0.b, z1.b }, z0.q[0]
// CHECK-ENCODING: [0x00,0xec,0x23,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4523ec00 <unknown>
aesdimc {z20.b-z21.b}, {z20.b-z21.b}, z10.q[2] // 01000101-00110011-11101101-01010100
// CHECK-INST: aesdimc { z20.b, z21.b }, { z20.b, z21.b }, z10.q[2]
// CHECK-ENCODING: [0x54,0xed,0x33,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4533ed54 <unknown>
aesdimc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3] // 01000101-00111011-11101111-11111110
// CHECK-INST: aesdimc { z30.b, z31.b }, { z30.b, z31.b }, z31.q[3]
// CHECK-ENCODING: [0xfe,0xef,0x3b,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453beffe <unknown>
// x4
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0] // 01000101-00100111-11101100-00000000
// CHECK-INST: aesdimc { z0.b - z3.b }, { z0.b - z3.b }, z0.q[0]
// CHECK-ENCODING: [0x00,0xec,0x27,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4527ec00 <unknown>
aesdimc {z20.b-z23.b}, {z20.b-z23.b}, z13.q[1] // 01000101-00101111-11101101-10110100
// CHECK-INST: aesdimc { z20.b - z23.b }, { z20.b - z23.b }, z13.q[1]
// CHECK-ENCODING: [0xb4,0xed,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 452fedb4 <unknown>
aesdimc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3] // 01000101-00111111-11101111-11111100
// CHECK-INST: aesdimc { z28.b - z31.b }, { z28.b - z31.b }, z31.q[3]
// CHECK-ENCODING: [0xfc,0xef,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453feffc <unknown>

12
llvm/test/MC/AArch64/SVE2p1/aese.s
View File

@@ -18,36 +18,36 @@
aese {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0] // 01000101-00100010-11101000-00000000
// CHECK-INST: aese { z0.b, z1.b }, { z0.b, z1.b }, z0.q[0]
// CHECK-ENCODING: [0x00,0xe8,0x22,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4522e800 <unknown>
aese {z20.b-z21.b}, {z20.b-z21.b}, z10.q[2] // 01000101-00110010-11101001-01010100
// CHECK-INST: aese { z20.b, z21.b }, { z20.b, z21.b }, z10.q[2]
// CHECK-ENCODING: [0x54,0xe9,0x32,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4532e954 <unknown>
aese {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3] // 01000101-00111010-11101011-11111110
// CHECK-INST: aese { z30.b, z31.b }, { z30.b, z31.b }, z31.q[3]
// CHECK-ENCODING: [0xfe,0xeb,0x3a,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453aebfe <unknown>
// x4
aese {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0] // 01000101-00100110-11101000-00000000
// CHECK-INST: aese { z0.b - z3.b }, { z0.b - z3.b }, z0.q[0]
// CHECK-ENCODING: [0x00,0xe8,0x26,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4526e800 <unknown>
aese {z20.b-z23.b}, {z20.b-z23.b}, z13.q[1] // 01000101-00101110-11101001-10110100
// CHECK-INST: aese { z20.b - z23.b }, { z20.b - z23.b }, z13.q[1]
// CHECK-ENCODING: [0xb4,0xe9,0x2e,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 452ee9b4 <unknown>
aese {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3] // 01000101-00111110-11101011-11111100
// CHECK-INST: aese { z28.b - z31.b }, { z28.b - z31.b }, z31.q[3]
// CHECK-ENCODING: [0xfc,0xeb,0x3e,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453eebfc <unknown>

12
llvm/test/MC/AArch64/SVE2p1/aesemc.s
View File

@@ -18,36 +18,36 @@
aesemc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0] // 01000101-00100011-11101000-00000000
// CHECK-INST: aesemc { z0.b, z1.b }, { z0.b, z1.b }, z0.q[0]
// CHECK-ENCODING: [0x00,0xe8,0x23,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4523e800 <unknown>
aesemc {z22.b-z23.b}, {z22.b-z23.b}, z13.q[1] // 01000101-00101011-11101001-10110110
// CHECK-INST: aesemc { z22.b, z23.b }, { z22.b, z23.b }, z13.q[1]
// CHECK-ENCODING: [0xb6,0xe9,0x2b,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 452be9b6 <unknown>
aesemc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3] // 01000101-00111011-11101011-11111110
// CHECK-INST: aesemc { z30.b, z31.b }, { z30.b, z31.b }, z31.q[3]
// CHECK-ENCODING: [0xfe,0xeb,0x3b,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453bebfe <unknown>
// x4
aesemc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0] // 01000101-00100111-11101000-00000000
// CHECK-INST: aesemc { z0.b - z3.b }, { z0.b - z3.b }, z0.q[0]
// CHECK-ENCODING: [0x00,0xe8,0x27,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4527e800 <unknown>
aesemc {z20.b-z23.b}, {z20.b-z23.b}, z10.q[2] // 01000101-00110111-11101001-01010100
// CHECK-INST: aesemc { z20.b - z23.b }, { z20.b - z23.b }, z10.q[2]
// CHECK-ENCODING: [0x54,0xe9,0x37,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4537e954 <unknown>
aesemc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3] // 01000101-00111111-11101011-11111100
// CHECK-INST: aesemc { z28.b - z31.b }, { z28.b - z31.b }, z31.q[3]
// CHECK-ENCODING: [0xfc,0xeb,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453febfc <unknown>

6
llvm/test/MC/AArch64/SVE2p1/pmlal.s
View File

@@ -17,17 +17,17 @@
pmlal {z0.q-z1.q}, z0.d, z0.d // 01000101-00100000-11111100-00000000
// CHECK-INST: pmlal { z0.q, z1.q }, z0.d, z0.d
// CHECK-ENCODING: [0x00,0xfc,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4520fc00 <unknown>
pmlal {z22.q-z23.q}, z13.d, z8.d // 01000101-00101000-11111101-10110110
// CHECK-INST: pmlal { z22.q, z23.q }, z13.d, z8.d
// CHECK-ENCODING: [0xb6,0xfd,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4528fdb6 <unknown>
pmlal {z30.q-z31.q}, z31.d, z31.d // 01000101-00111111-11111111-11111110
// CHECK-INST: pmlal { z30.q, z31.q }, z31.d, z31.d
// CHECK-ENCODING: [0xfe,0xff,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453ffffe <unknown>

6
llvm/test/MC/AArch64/SVE2p1/pmull.s
View File

@@ -17,17 +17,17 @@
pmull {z0.q-z1.q}, z0.d, z0.d // 01000101-00100000-11111000-00000000
// CHECK-INST: pmull { z0.q, z1.q }, z0.d, z0.d
// CHECK-ENCODING: [0x00,0xf8,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4520f800 <unknown>
pmull {z22.q-z23.q}, z13.d, z8.d // 01000101-00101000-11111001-10110110
// CHECK-INST: pmull { z22.q, z23.q }, z13.d, z8.d
// CHECK-ENCODING: [0xb6,0xf9,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 4528f9b6 <unknown>
pmull {z30.q-z31.q}, z31.d, z31.d // 01000101-00111111-11111011-11111110
// CHECK-INST: pmull { z30.q, z31.q }, z31.d, z31.d
// CHECK-ENCODING: [0xfe,0xfb,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2 or ssve-aes sve-aes2
// CHECK-ERROR: instruction requires: sve or ssve-aes sve-aes2
// CHECK-UNKNOWN: 453ffbfe <unknown>

10
llvm/unittests/TargetParser/TargetParserTest.cpp
View File

@@ -1440,7 +1440,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_PCDPHINT, AArch64::AEK_POPS,
AArch64::AEK_SVEAES, AArch64::AEK_SME_MOP4,
AArch64::AEK_SME_TMOP, AArch64::AEK_SVEBITPERM,
AArch64::AEK_SSVE_BITPERM,
AArch64::AEK_SSVE_BITPERM, AArch64::AEK_SVESHA3,
};
std::vector<StringRef> Features;
@@ -1479,6 +1479,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+sve-aes"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-aes"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sm4"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve-sha3"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sha3"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve-bitperm"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-bitperm"));
@@ -1651,6 +1652,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"sve-f16f32mm", "nosve-f16f32mm", "+sve-f16f32mm", "-sve-f16f32mm"},
{"sve2", "nosve2", "+sve2", "-sve2"},
{"sve-aes", "nosve-aes", "+sve-aes", "-sve-aes"},
{"sve-sha3", "nosve-sha3", "+sve-sha3", "-sve-sha3"},
{"sve2-aes", "nosve2-aes", "+sve2-aes", "-sve2-aes"},
{"sve2-sm4", "nosve2-sm4", "+sve2-sm4", "-sve2-sm4"},
{"sve2-sha3", "nosve2-sha3", "+sve2-sha3", "-sve2-sha3"},
@@ -2159,6 +2161,12 @@ AArch64ExtensionDependenciesBaseArchTestParams
{"sve2"},
{"sve2-aes", "sve-aes"}},
// -sve2-sha3 should disable sve-sha3 (only)
{AArch64::ARMV9_6A,
{"sve2", "sve-sha3", "nosve2-sha3"},
{"sve2"},
{"sve2-sha3", "sve-sha3"}},
// sme-tmop -> sme
{AArch64::ARMV8A, {"nosme2", "sme-tmop"}, {"sme2", "sme-tmop"}, {}},
{AArch64::ARMV8A, {"sme-tmop", "nosme2"}, {}, {"sme2", "sme-tmop"}},