[AMDGPU] Fold more AGPR copies/PHIs in SIFoldOperands
Generalize `tryFoldLCSSAPhi` into `tryFoldPhiAGPR` which works on any kind of PHI node (not just LCSSA ones) and attempts to create AGPR Phis more aggressively. Also adds a GFX908-only "cleanup" function `tryOptimizeAGPRPhis` which tries to minimize AGPR to AGPR copies on GFX908, which doesn't have a ACCVGPR MOV instruction (so AGPR-AGPR copies become 2 or 3 instructions as they need a VGPR temp). The reason why this is needed is because D143731 + the new `tryFoldPhiAGPR` may create a lot more PHIs (one 32xfloat PHI becomes 32 float phis), and if each PHI hits the same AGPR (like in `test_mfma_loop_agpr_init`) they will be lowered to 32 copies from the same AGPR, which will each become 2-3 instructions. Creating a VGPR cache in this case prevents all those copies from being generated (we have AGPR-VGPR copies instead which are trivial). This is a prepation patch intended to prevent regressions in D143731 when AGPRs are involved. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D144099
This commit is contained in:
pvanhout
@@ -111,9 +111,11 @@ public:
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std::pair<const MachineOperand *, int> isOMod(const MachineInstr &MI) const;
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bool tryFoldOMod(MachineInstr &MI);
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bool tryFoldRegSequence(MachineInstr &MI);
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bool tryFoldLCSSAPhi(MachineInstr &MI);
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bool tryFoldPhiAGPR(MachineInstr &MI);
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bool tryFoldLoad(MachineInstr &MI);
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bool tryOptimizeAGPRPhis(MachineBasicBlock &MBB);
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public:
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SIFoldOperands() : MachineFunctionPass(ID) {
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initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
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@@ -138,6 +140,16 @@ char SIFoldOperands::ID = 0;
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char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
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static const TargetRegisterClass *getRegOpRC(const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const MachineOperand &MO) {
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const TargetRegisterClass *RC = MRI.getRegClass(MO.getReg());
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if (const TargetRegisterClass *SubRC =
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TRI.getSubRegisterClass(RC, MO.getSubReg()))
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RC = SubRC;
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return RC;
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}
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// Map multiply-accumulate opcode to corresponding multiply-add opcode if any.
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static unsigned macToMad(unsigned Opc) {
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switch (Opc) {
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@@ -1631,52 +1643,133 @@ bool SIFoldOperands::tryFoldRegSequence(MachineInstr &MI) {
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return true;
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}
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// Try to hoist an AGPR to VGPR copy out of the loop across a LCSSA PHI.
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// Try to hoist an AGPR to VGPR copy across a PHI.
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// This should allow folding of an AGPR into a consumer which may support it.
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// I.e.:
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//
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// loop: // loop:
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// %1:vreg = COPY %0:areg // exit:
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// exit: => // %1:areg = PHI %0:areg, %loop
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// %2:vreg = PHI %1:vreg, %loop // %2:vreg = COPY %1:areg
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bool SIFoldOperands::tryFoldLCSSAPhi(MachineInstr &PHI) {
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// Example 1: LCSSA PHI
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// loop:
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// %1:vreg = COPY %0:areg
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// exit:
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// %2:vreg = PHI %1:vreg, %loop
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// =>
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// loop:
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// exit:
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// %1:areg = PHI %0:areg, %loop
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// %2:vreg = COPY %1:areg
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//
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// Example 2: PHI with multiple incoming values:
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// entry:
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// %1:vreg = GLOBAL_LOAD(..)
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// loop:
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// %2:vreg = PHI %1:vreg, %entry, %5:vreg, %loop
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// %3:areg = COPY %2:vreg
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// %4:areg = (instr using %3:areg)
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// %5:vreg = COPY %4:areg
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// =>
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// entry:
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// %1:vreg = GLOBAL_LOAD(..)
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// %2:areg = COPY %1:vreg
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// loop:
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// %3:areg = PHI %2:areg, %entry, %X:areg,
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// %4:areg = (instr using %3:areg)
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bool SIFoldOperands::tryFoldPhiAGPR(MachineInstr &PHI) {
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assert(PHI.isPHI());
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if (PHI.getNumExplicitOperands() != 3) // Single input LCSSA PHI
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return false;
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Register PhiIn = PHI.getOperand(1).getReg();
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Register PhiOut = PHI.getOperand(0).getReg();
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if (PHI.getOperand(1).getSubReg() ||
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!TRI->isVGPR(*MRI, PhiIn) || !TRI->isVGPR(*MRI, PhiOut))
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if (!TRI->isVGPR(*MRI, PhiOut))
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return false;
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// A single use should not matter for correctness, but if it has another use
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// inside the loop we may perform copy twice in a worst case.
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if (!MRI->hasOneNonDBGUse(PhiIn))
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// Iterate once over all incoming values of the PHI to check if this PHI is
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// eligible, and determine the exact AGPR RC we'll target.
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const TargetRegisterClass *ARC = nullptr;
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for (unsigned K = 1; K < PHI.getNumExplicitOperands(); K += 2) {
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MachineOperand &MO = PHI.getOperand(K);
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Register PhiIn = MO.getReg();
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if (MO.getSubReg() || !TRI->isVGPR(*MRI, PhiIn))
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return false;
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MachineInstr *Copy = MRI->getVRegDef(PhiIn);
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if (!Copy || !Copy->isCopy())
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continue;
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Register CopyIn = Copy->getOperand(1).getReg();
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if (CopyIn.isVirtual() && TRI->isAGPR(*MRI, CopyIn)) {
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const TargetRegisterClass *CopyInRC =
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getRegOpRC(*MRI, *TRI, Copy->getOperand(1));
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if (ARC && !ARC->hasSubClassEq(CopyInRC))
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return false;
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ARC = CopyInRC;
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}
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}
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if (!ARC)
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return false;
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MachineInstr *Copy = MRI->getVRegDef(PhiIn);
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if (!Copy || !Copy->isCopy())
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return false;
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// Rewrite the PHI's incoming values to ARC.
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LLVM_DEBUG(dbgs() << "Folding AGPR copies into: " << PHI);
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for (unsigned K = 1; K < PHI.getNumExplicitOperands(); K += 2) {
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MachineOperand &MO = PHI.getOperand(K);
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Register Reg = MO.getReg();
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Register CopyIn = Copy->getOperand(1).getReg();
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if (!TRI->isAGPR(*MRI, CopyIn) || Copy->getOperand(1).getSubReg())
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return false;
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MachineBasicBlock::iterator InsertPt;
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MachineBasicBlock *InsertMBB = nullptr;
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const TargetRegisterClass *ARC = MRI->getRegClass(CopyIn);
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// Look at the def of Reg, ignoring all copies.
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bool UseAccVGPRWrite = false;
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if (MachineInstr *Def = MRI->getVRegDef(Reg)) {
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// Look at pre-existing COPY instructions from ARC: Steal the operand. If
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// the copy was single-use, it will be removed by DCE later.
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if (Def->isCopy()) {
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MachineOperand &CopyIn = Def->getOperand(1);
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if (CopyIn.getReg().isVirtual() &&
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getRegOpRC(*MRI, *TRI, CopyIn)->hasSubClassEq(ARC)) {
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MO.setReg(CopyIn.getReg());
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MO.setSubReg(CopyIn.getSubReg());
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continue;
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}
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// If this is a multi-use SGPR -> VGPR copy, use V_ACCVGPR_WRITE on
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// GFX908 directly instead of a COPY. Otherwise, SIFoldOperand may try
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// to fold the sgpr -> vgpr -> agpr copy into a sgpr -> agpr copy which
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// is unlikely to be profitable.
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if (!ST->hasGFX90AInsts() && !MRI->hasOneNonDBGUse(Reg) &&
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TRI->isSGPRReg(*MRI, CopyIn.getReg()))
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UseAccVGPRWrite = true;
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}
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InsertPt = ++Def->getIterator();
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InsertMBB = Def->getParent();
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} else {
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InsertMBB = PHI.getOperand(MO.getOperandNo() + 1).getMBB();
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InsertPt = InsertMBB->getFirstTerminator();
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}
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const unsigned CopyOpc =
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UseAccVGPRWrite ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 : AMDGPU::COPY;
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Register NewReg = MRI->createVirtualRegister(ARC);
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MachineInstr *MI = BuildMI(*InsertMBB, InsertPt, PHI.getDebugLoc(),
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TII->get(CopyOpc), NewReg)
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.addReg(Reg);
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MO.setReg(NewReg);
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(void)MI;
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LLVM_DEBUG(dbgs() << " Created COPY: " << *MI);
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}
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// Replace the PHI's result with a new register.
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Register NewReg = MRI->createVirtualRegister(ARC);
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PHI.getOperand(1).setReg(CopyIn);
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PHI.getOperand(0).setReg(NewReg);
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// COPY that new register back to the original PhiOut register. This COPY will
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// usually be folded out later.
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MachineBasicBlock *MBB = PHI.getParent();
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BuildMI(*MBB, MBB->getFirstNonPHI(), Copy->getDebugLoc(),
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BuildMI(*MBB, MBB->getFirstNonPHI(), PHI.getDebugLoc(),
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TII->get(AMDGPU::COPY), PhiOut)
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.addReg(NewReg, RegState::Kill);
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Copy->eraseFromParent(); // We know this copy had a single use.
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LLVM_DEBUG(dbgs() << "Folded " << PHI);
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.addReg(NewReg);
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LLVM_DEBUG(dbgs() << " Done: Folded " << PHI);
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return true;
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}
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@@ -1736,6 +1829,101 @@ bool SIFoldOperands::tryFoldLoad(MachineInstr &MI) {
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return true;
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}
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// tryFoldPhiAGPR will aggressively try to create AGPR PHIs.
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// For GFX90A and later, this is pretty much always a good thing, but for GFX908
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// there's cases where it can create a lot more AGPR-AGPR copies, which are
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// expensive on this architecture due to the lack of V_ACCVGPR_MOV.
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//
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// This function looks at all AGPR PHIs in a basic block and collects their
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// operands. Then, it checks for register that are used more than once across
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// all PHIs and caches them in a VGPR. This prevents ExpandPostRAPseudo from
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// having to create one VGPR temporary per use, which can get very messy if
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// these PHIs come from a broken-up large PHI (e.g. 32 AGPR phis, one per vector
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// element).
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//
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// Example
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// a:
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// %in:agpr_256 = COPY %foo:vgpr_256
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// c:
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// %x:agpr_32 = ..
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// b:
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// %0:areg = PHI %in.sub0:agpr_32, %a, %x, %c
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// %1:areg = PHI %in.sub0:agpr_32, %a, %y, %c
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// %2:areg = PHI %in.sub0:agpr_32, %a, %z, %c
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// =>
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// a:
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// %in:agpr_256 = COPY %foo:vgpr_256
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// %tmp:vgpr_32 = V_ACCVGPR_READ_B32_e64 %in.sub0:agpr_32
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// %tmp_agpr:agpr_32 = COPY %tmp
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// c:
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// %x:agpr_32 = ..
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// b:
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// %0:areg = PHI %tmp_agpr, %a, %x, %c
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// %1:areg = PHI %tmp_agpr, %a, %y, %c
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// %2:areg = PHI %tmp_agpr, %a, %z, %c
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bool SIFoldOperands::tryOptimizeAGPRPhis(MachineBasicBlock &MBB) {
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// This is only really needed on GFX908 where AGPR-AGPR copies are
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// unreasonably difficult.
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if (ST->hasGFX90AInsts())
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return false;
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// Look at all AGPR Phis and collect the register + subregister used.
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DenseMap<std::pair<Register, unsigned>, std::vector<MachineOperand *>>
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RegToMO;
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for (auto &MI : MBB) {
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if (!MI.isPHI())
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break;
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if (!TRI->isAGPR(*MRI, MI.getOperand(0).getReg()))
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continue;
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for (unsigned K = 1; K < MI.getNumOperands(); K += 2) {
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MachineOperand &PhiMO = MI.getOperand(K);
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RegToMO[{PhiMO.getReg(), PhiMO.getSubReg()}].push_back(&PhiMO);
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}
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}
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// For all (Reg, SubReg) pair that are used more than once, cache the value in
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// a VGPR.
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bool Changed = false;
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for (const auto &[Entry, MOs] : RegToMO) {
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if (MOs.size() == 1)
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continue;
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const auto [Reg, SubReg] = Entry;
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MachineInstr *Def = MRI->getVRegDef(Reg);
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MachineBasicBlock *DefMBB = Def->getParent();
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// Create a copy in a VGPR using V_ACCVGPR_READ_B32_e64 so it's not folded
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// out.
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const TargetRegisterClass *ARC = getRegOpRC(*MRI, *TRI, *MOs.front());
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Register TempVGPR =
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MRI->createVirtualRegister(TRI->getEquivalentVGPRClass(ARC));
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MachineInstr *VGPRCopy =
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BuildMI(*DefMBB, ++Def->getIterator(), Def->getDebugLoc(),
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TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64), TempVGPR)
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.addReg(Reg, /* flags */ 0, SubReg);
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// Copy back to an AGPR and use that instead of the AGPR subreg in all MOs.
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Register TempAGPR = MRI->createVirtualRegister(ARC);
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BuildMI(*DefMBB, ++VGPRCopy->getIterator(), Def->getDebugLoc(),
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TII->get(AMDGPU::COPY), TempAGPR)
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.addReg(TempVGPR);
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LLVM_DEBUG(dbgs() << "Caching AGPR into VGPR: " << *VGPRCopy);
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for (MachineOperand *MO : MOs) {
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MO->setReg(TempAGPR);
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MO->setSubReg(AMDGPU::NoSubRegister);
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LLVM_DEBUG(dbgs() << " Changed PHI Operand: " << *MO << "\n");
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}
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Changed = true;
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}
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return Changed;
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}
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bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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@@ -1769,7 +1957,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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continue;
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}
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if (MI.isPHI() && tryFoldLCSSAPhi(MI)) {
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if (MI.isPHI() && tryFoldPhiAGPR(MI)) {
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Changed = true;
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continue;
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}
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@@ -1794,6 +1982,8 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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!tryFoldOMod(MI))
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Changed |= tryFoldClamp(MI);
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}
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Changed |= tryOptimizeAGPRPhis(*MBB);
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}
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return Changed;
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410
llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
Normal file
410
llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
Normal file
@@ -0,0 +1,410 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX908
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# RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
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# RUN: llc -march=amdgcn -mcpu=gfx940 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s --check-prefixes=GFX90A
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---
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name: test_sgpr_init_multiuse
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tracksRegLiveness: true
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body: |
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; GFX908-LABEL: name: test_sgpr_init_multiuse
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; GFX908: bb.0:
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; GFX908-NEXT: successors: %bb.1(0x80000000)
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; GFX908-NEXT: liveins: $sgpr0, $scc
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; GFX908-NEXT: {{ $}}
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; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GFX908-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
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; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY1]], implicit $exec
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; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY1]], implicit $exec
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; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY1]], implicit $exec
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; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY1]], implicit $exec
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; GFX908-NEXT: {{ $}}
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; GFX908-NEXT: bb.1:
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; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GFX908-NEXT: liveins: $scc
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; GFX908-NEXT: {{ $}}
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; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_3]], %bb.0, %13.sub0, %bb.1
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; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_2]], %bb.0, %13.sub1, %bb.1
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; GFX908-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_1]], %bb.0, %13.sub2, %bb.1
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; GFX908-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_]], %bb.0, %13.sub3, %bb.1
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; GFX908-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
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; GFX908-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
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; GFX908-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
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; GFX908-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
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; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY2]], %subreg.sub3
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; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
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; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
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; GFX908-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
|
||||
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: S_ENDPGM 0
|
||||
; GFX90A-LABEL: name: test_sgpr_init_multiuse
|
||||
; GFX90A: bb.0:
|
||||
; GFX90A-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX90A-NEXT: liveins: $sgpr0, $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
|
||||
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
|
||||
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
|
||||
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
|
||||
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.1:
|
||||
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GFX90A-NEXT: liveins: $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY5]], %bb.0, %13.sub0, %bb.1
|
||||
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %13.sub1, %bb.1
|
||||
; GFX90A-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %13.sub2, %bb.1
|
||||
; GFX90A-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %13.sub3, %bb.1
|
||||
; GFX90A-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
|
||||
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
|
||||
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
|
||||
; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
|
||||
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY8]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY6]], %subreg.sub3
|
||||
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
; GFX90A-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
|
||||
; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $sgpr0, $scc
|
||||
successors: %bb.1
|
||||
|
||||
%0:sgpr_32 = COPY $sgpr0
|
||||
%1:vgpr_32 = COPY %0
|
||||
|
||||
bb.1:
|
||||
liveins: $scc
|
||||
successors: %bb.1, %bb.2
|
||||
|
||||
%8:vgpr_32 = PHI %1, %bb.0, %16, %bb.1
|
||||
%9:vgpr_32 = PHI %1, %bb.0, %17, %bb.1
|
||||
%10:vgpr_32 = PHI %1, %bb.0, %18, %bb.1
|
||||
%11:vgpr_32 = PHI %1, %bb.0, %19, %bb.1
|
||||
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
|
||||
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
%15:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %14:vgpr_32, %13:vgpr_32, %12:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
|
||||
%16:vgpr_32 = COPY %15.sub0
|
||||
%17:vgpr_32 = COPY %15.sub1
|
||||
%18:vgpr_32 = COPY %15.sub2
|
||||
%19:vgpr_32 = COPY %15.sub3
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
name: test_sgpr_init_singleuse
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
; GFX908-LABEL: name: test_sgpr_init_singleuse
|
||||
; GFX908: bb.0:
|
||||
; GFX908-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX908-NEXT: liveins: $sgpr0, $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
|
||||
; GFX908-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX908-NEXT: [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
|
||||
; GFX908-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX908-NEXT: [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY3]]
|
||||
; GFX908-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX908-NEXT: [[COPY6:%[0-9]+]]:agpr_32 = COPY [[COPY5]]
|
||||
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX908-NEXT: [[COPY8:%[0-9]+]]:agpr_32 = COPY [[COPY7]]
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.1:
|
||||
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GFX908-NEXT: liveins: $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %16.sub0, %bb.1
|
||||
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %16.sub1, %bb.1
|
||||
; GFX908-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY6]], %bb.0, %16.sub2, %bb.1
|
||||
; GFX908-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY8]], %bb.0, %16.sub3, %bb.1
|
||||
; GFX908-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
|
||||
; GFX908-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
|
||||
; GFX908-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
|
||||
; GFX908-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
|
||||
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY12]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY9]], %subreg.sub3
|
||||
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
; GFX908-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
|
||||
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: S_ENDPGM 0
|
||||
; GFX90A-LABEL: name: test_sgpr_init_singleuse
|
||||
; GFX90A: bb.0:
|
||||
; GFX90A-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX90A-NEXT: liveins: $sgpr0, $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
|
||||
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY1]]
|
||||
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY3]]
|
||||
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: [[COPY6:%[0-9]+]]:agpr_32 = COPY [[COPY5]]
|
||||
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:agpr_32 = COPY [[COPY7]]
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.1:
|
||||
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GFX90A-NEXT: liveins: $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %16.sub0, %bb.1
|
||||
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %16.sub1, %bb.1
|
||||
; GFX90A-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY6]], %bb.0, %16.sub2, %bb.1
|
||||
; GFX90A-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY8]], %bb.0, %16.sub3, %bb.1
|
||||
; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
|
||||
; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
|
||||
; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
|
||||
; GFX90A-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
|
||||
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY12]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY9]], %subreg.sub3
|
||||
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
; GFX90A-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
|
||||
; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $sgpr0, $scc
|
||||
successors: %bb.1
|
||||
|
||||
%0:sgpr_32 = COPY $sgpr0
|
||||
%1:vgpr_32 = COPY %0
|
||||
%2:vgpr_32 = COPY %0
|
||||
%3:vgpr_32 = COPY %0
|
||||
%4:vgpr_32 = COPY %0
|
||||
|
||||
bb.1:
|
||||
liveins: $scc
|
||||
successors: %bb.1, %bb.2
|
||||
|
||||
%8:vgpr_32 = PHI %1, %bb.0, %16, %bb.1
|
||||
%9:vgpr_32 = PHI %2, %bb.0, %17, %bb.1
|
||||
%10:vgpr_32 = PHI %3, %bb.0, %18, %bb.1
|
||||
%11:vgpr_32 = PHI %4, %bb.0, %19, %bb.1
|
||||
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
|
||||
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
%15:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %14:vgpr_32, %13:vgpr_32, %12:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
|
||||
%16:vgpr_32 = COPY %15.sub0
|
||||
%17:vgpr_32 = COPY %15.sub1
|
||||
%18:vgpr_32 = COPY %15.sub2
|
||||
%19:vgpr_32 = COPY %15.sub3
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
name: test_vgpr_init
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
; GFX908-LABEL: name: test_vgpr_init
|
||||
; GFX908: bb.0:
|
||||
; GFX908-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX908-NEXT: liveins: $vgpr0, $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX908-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
|
||||
; GFX908-NEXT: [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY]]
|
||||
; GFX908-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[COPY]]
|
||||
; GFX908-NEXT: [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY]]
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.1:
|
||||
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GFX908-NEXT: liveins: $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
|
||||
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
|
||||
; GFX908-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %12.sub2, %bb.1
|
||||
; GFX908-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %12.sub3, %bb.1
|
||||
; GFX908-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
|
||||
; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
|
||||
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
|
||||
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
|
||||
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
|
||||
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
; GFX908-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
|
||||
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: S_ENDPGM 0
|
||||
; GFX90A-LABEL: name: test_vgpr_init
|
||||
; GFX90A: bb.0:
|
||||
; GFX90A-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: [[COPY2:%[0-9]+]]:agpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:agpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.1:
|
||||
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GFX90A-NEXT: liveins: $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
|
||||
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
|
||||
; GFX90A-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %12.sub2, %bb.1
|
||||
; GFX90A-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %12.sub3, %bb.1
|
||||
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
|
||||
; GFX90A-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
|
||||
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
|
||||
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
|
||||
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
|
||||
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
; GFX90A-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
|
||||
; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $vgpr0, $scc
|
||||
successors: %bb.1
|
||||
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
|
||||
bb.1:
|
||||
liveins: $scc
|
||||
successors: %bb.1, %bb.2
|
||||
|
||||
%8:vgpr_32 = PHI %0, %bb.0, %16, %bb.1
|
||||
%9:vgpr_32 = PHI %0, %bb.0, %17, %bb.1
|
||||
%10:vgpr_32 = PHI %0, %bb.0, %18, %bb.1
|
||||
%11:vgpr_32 = PHI %0, %bb.0, %19, %bb.1
|
||||
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
|
||||
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
%15:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %14:vgpr_32, %13:vgpr_32, %12:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
|
||||
%16:vgpr_32 = COPY %15.sub0
|
||||
%17:vgpr_32 = COPY %15.sub1
|
||||
%18:vgpr_32 = COPY %15.sub2
|
||||
%19:vgpr_32 = COPY %15.sub3
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
name: test_use_vgpr_temp
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
; GFX908-LABEL: name: test_use_vgpr_temp
|
||||
; GFX908: bb.0:
|
||||
; GFX908-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX908-NEXT: liveins: $sgpr0, $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
|
||||
; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
|
||||
; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
|
||||
; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
|
||||
; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
|
||||
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
|
||||
; GFX908-NEXT: [[V_ACCVGPR_READ_B32_e64_:%[0-9]+]]:vgpr_32 = V_ACCVGPR_READ_B32_e64 [[REG_SEQUENCE]].sub0, implicit $exec
|
||||
; GFX908-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[V_ACCVGPR_READ_B32_e64_]]
|
||||
; GFX908-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.1:
|
||||
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GFX908-NEXT: liveins: $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub0, %bb.1
|
||||
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub1, %bb.1
|
||||
; GFX908-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub2, %bb.1
|
||||
; GFX908-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub3, %bb.1
|
||||
; GFX908-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
|
||||
; GFX908-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
|
||||
; GFX908-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
|
||||
; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
|
||||
; GFX908-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
; GFX908-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE1]], 0, 0, 0, implicit $mode, implicit $exec
|
||||
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: S_ENDPGM 0
|
||||
; GFX90A-LABEL: name: test_use_vgpr_temp
|
||||
; GFX90A: bb.0:
|
||||
; GFX90A-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX90A-NEXT: liveins: $sgpr0, $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
|
||||
; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
|
||||
; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
|
||||
; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
|
||||
; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
|
||||
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
|
||||
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.1:
|
||||
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GFX90A-NEXT: liveins: $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub0, %bb.1
|
||||
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub1, %bb.1
|
||||
; GFX90A-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub2, %bb.1
|
||||
; GFX90A-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub3, %bb.1
|
||||
; GFX90A-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
|
||||
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
|
||||
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
|
||||
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
|
||||
; GFX90A-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY2]], %subreg.sub3
|
||||
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
; GFX90A-NEXT: [[V_MFMA_F32_4X4X1F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE1]], 0, 0, 0, implicit $mode, implicit $exec
|
||||
; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: S_ENDPGM 0
|
||||
bb.0:
|
||||
; Tests that tryOptimizeAGPRPhis kicks in for GFX908.
|
||||
liveins: $sgpr0, $scc
|
||||
successors: %bb.1
|
||||
|
||||
%1:vgpr_32 = COPY $sgpr0
|
||||
%2:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %1, implicit $exec
|
||||
%3:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %1, implicit $exec
|
||||
%4:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %1, implicit $exec
|
||||
%5:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %1, implicit $exec
|
||||
%6:areg_128_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1, %4, %subreg.sub2, %5, %subreg.sub3
|
||||
%7:vgpr_32 = COPY %6.sub0
|
||||
bb.1:
|
||||
liveins: $scc
|
||||
successors: %bb.1, %bb.2
|
||||
|
||||
%8:vgpr_32 = PHI %7, %bb.0, %16, %bb.1
|
||||
%9:vgpr_32 = PHI %7, %bb.0, %17, %bb.1
|
||||
%10:vgpr_32 = PHI %7, %bb.0, %18, %bb.1
|
||||
%11:vgpr_32 = PHI %7, %bb.0, %19, %bb.1
|
||||
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
|
||||
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
|
||||
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
|
||||
%15:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %14:vgpr_32, %13:vgpr_32, %12:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
|
||||
%16:vgpr_32 = COPY %15.sub0
|
||||
%17:vgpr_32 = COPY %15.sub1
|
||||
%18:vgpr_32 = COPY %15.sub2
|
||||
%19:vgpr_32 = COPY %15.sub3
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
Reference in New Issue
Block a user