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[LLVM][SVE] Ensure all fixed length mask bits are defined. (#116819)

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convertFixedMaskToScalableVector expects the mask input to honour the
BoolContents scheme employed by the target. For AArch64 this means a
mask should be zero or all ones, and thus when promoting a mask we must
use a sign extend.
This commit is contained in:
Paul Walker
2024-11-20 13:54:50 +00:00
committed by GitHub
parent b17f607703
commit 71b87d1267
2 changed files with 3 additions and 3 deletions
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2
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@@ -28163,7 +28163,7 @@ SDValue AArch64TargetLowering::LowerFixedLengthVectorMLoadToSVE(
if (VT.getScalarSizeInBits() > Mask.getValueType().getScalarSizeInBits()) {
assert(Load->getExtensionType() != ISD::NON_EXTLOAD &&
"Incorrect mask type");
Mask = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Mask);
Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Mask);
}
Mask = convertFixedMaskToScalableVector(Mask, DAG);

4
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
View File

@@ -2677,7 +2677,7 @@ define <3 x i32> @masked_load_zext_v3i32(ptr %load_ptr, <3 x i1> %pm) {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: lsl z0.h, z0.h, #15
; CHECK-NEXT: asr z0.h, z0.h, #15
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: sunpklo z0.s, z0.h
; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
@@ -2750,7 +2750,7 @@ define <3 x i32> @masked_load_sext_v3i32(ptr %load_ptr, <3 x i1> %pm) {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: lsl z0.h, z0.h, #15
; CHECK-NEXT: asr z0.h, z0.h, #15
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: sunpklo z0.s, z0.h
; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0
; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0