[AMDGPU] Fix undefined scc register in successor block of SI_KILL terminators (#134718)
Fix issue 131298 where an undefined $scc register causes verifier errors when using SI_KILL_F32_COND_IMM_TERMINATOR instructions. The problem occurs because the $scc register defined in a comparison before the kill terminator is used in successor blocks, but was not properly marked as live-in. This patch: - Adds code to check if SCC is used in the successor block - Adds SCC as a live-in to successor blocks - Handles both explicit and implicit uses of SCC With this patch the machine verifier no longer reports undefined $scc errors in following kill terminator instruction. Fixes #131298 --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
This commit is contained in:
mssefat
@@ -47,6 +47,8 @@ static std::pair<bool, bool> runImpl(MachineFunction &MF) {
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
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TLI->finalizeLowering(MF);
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// Iterate through each instruction in the function, looking for pseudos.
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock *MBB = &*I;
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@@ -74,9 +76,6 @@ static std::pair<bool, bool> runImpl(MachineFunction &MF) {
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}
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}
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}
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TLI->finalizeLowering(MF);
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return {Changed, PreserveCFG};
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}
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@@ -4513,7 +4513,7 @@ Register SITargetLowering::getRegisterByName(const char *RegName, LLT VT,
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MachineBasicBlock *
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SITargetLowering::splitKillBlock(MachineInstr &MI,
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MachineBasicBlock *BB) const {
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MachineBasicBlock *SplitBB = BB->splitAt(MI, false /*UpdateLiveIns*/);
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MachineBasicBlock *SplitBB = BB->splitAt(MI, /*UpdateLiveIns=*/true);
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const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
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MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
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return SplitBB;
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73
llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
Normal file
73
llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
Normal file
@@ -0,0 +1,73 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -run-pass finalize-isel -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: phi_use_def_before_kill
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: phi_use_def_before_kill
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 1065353216
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; CHECK-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY1]], 0, killed [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; CHECK-NEXT: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_GT_F32_e64 0, [[V_ADD_F32_e64_]], 0, [[S_MOV_B32_1]], 0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 -1082130432
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed [[S_MOV_B32_2]]
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; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[S_MOV_B32_1]], 0, [[COPY2]], killed [[V_CMP_GT_F32_e64_]], implicit $exec
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY [[V_CNDMASK_B32_e64_]]
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; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; CHECK-NEXT: S_CMP_LG_U32 [[COPY]], killed [[S_MOV_B32_3]], implicit-def $scc
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; CHECK-NEXT: SI_KILL_F32_COND_IMM_TERMINATOR [[V_ADD_F32_e64_]], 0, 2, implicit-def $vcc_lo, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $vcc_lo, $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; CHECK-NEXT: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, killed [[S_MOV_B32_4]], 0, implicit $mode, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; CHECK-NEXT: [[V_CMP_EQ_F32_e64_1:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, killed [[S_MOV_B32_5]], 0, implicit $mode, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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liveins: $sgpr0, $sgpr1
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%3:sgpr_32 = COPY $sgpr1
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%2:sgpr_32 = COPY $sgpr0
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%5:sgpr_32 = S_MOV_B32 1065353216
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%6:vgpr_32 = nofpexcept V_ADD_F32_e64 0, %2:sgpr_32, 0, killed %5:sgpr_32, 0, 0, implicit $mode, implicit $exec
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%7:sgpr_32 = S_MOV_B32 0
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%8:sreg_32_xm0_xexec = nofpexcept V_CMP_GT_F32_e64 0, %6:vgpr_32, 0, %7:sgpr_32, 0, implicit $mode, implicit $exec
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%9:sgpr_32 = S_MOV_B32 -1082130432
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%11:vgpr_32 = COPY killed %9:sgpr_32
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%10:vgpr_32 = V_CNDMASK_B32_e64 0, %7:sgpr_32, 0, %11:vgpr_32, killed %8:sreg_32_xm0_xexec, implicit $exec
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%0:sgpr_32 = COPY %10:vgpr_32
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%12:sreg_32 = S_MOV_B32 0
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S_CMP_LG_U32 %3:sgpr_32, killed %12:sreg_32, implicit-def $scc
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SI_KILL_F32_COND_IMM_PSEUDO %6:vgpr_32, 0, 2, implicit-def $vcc, implicit $exec
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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S_BRANCH %bb.2
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bb.1:
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%13:sgpr_32 = S_MOV_B32 0
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%14:sreg_32 = nofpexcept V_CMP_EQ_F32_e64 0, %3:sgpr_32, 0, killed %13:sgpr_32, 0, implicit $mode, implicit $exec
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S_ENDPGM 0
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bb.2:
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%15:sgpr_32 = S_MOV_B32 0
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%16:sreg_32 = nofpexcept V_CMP_EQ_F32_e64 0, %3:sgpr_32, 0, killed %15:sgpr_32, 0, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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@@ -1956,6 +1956,165 @@ bb.1:
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ret void
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}
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define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0 {
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; SI-LABEL: scc_use_after_kill_inst:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: v_add_f32_e64 v1, s0, 1.0
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; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
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; SI-NEXT: s_mov_b64 s[2:3], exec
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; SI-NEXT: s_cmp_lg_u32 s1, 0
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; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
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; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1
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; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc
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; SI-NEXT: s_cbranch_scc0 .LBB17_6
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; SI-NEXT: ; %bb.1: ; %bb
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; SI-NEXT: s_andn2_b64 exec, exec, vcc
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; SI-NEXT: s_cbranch_scc0 .LBB17_3
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; SI-NEXT: ; %bb.2: ; %bb8
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 8
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, 4.0
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; SI-NEXT: .LBB17_3: ; %phibb
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; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
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; SI-NEXT: s_cbranch_vccz .LBB17_5
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; SI-NEXT: ; %bb.4: ; %bb10
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 9
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: .LBB17_5: ; %end
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; SI-NEXT: s_endpgm
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; SI-NEXT: .LBB17_6:
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; SI-NEXT: s_mov_b64 exec, 0
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; SI-NEXT: exp null off, off, off, off done vm
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; SI-NEXT: s_endpgm
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;
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; GFX10-WAVE64-LABEL: scc_use_after_kill_inst:
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; GFX10-WAVE64: ; %bb.0: ; %bb
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; GFX10-WAVE64-NEXT: v_add_f32_e64 v1, s0, 1.0
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; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec
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; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s1, 0
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; GFX10-WAVE64-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
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; GFX10-WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
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; GFX10-WAVE64-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1
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; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc
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; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB17_6
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; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb
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; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc
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; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB17_3
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; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb8
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; GFX10-WAVE64-NEXT: v_mov_b32_e32 v1, 8
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; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 4.0
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; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v1, off
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; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-WAVE64-NEXT: .LBB17_3: ; %phibb
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; GFX10-WAVE64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
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; GFX10-WAVE64-NEXT: s_cbranch_vccz .LBB17_5
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; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb10
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; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 9
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; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off
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; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-WAVE64-NEXT: .LBB17_5: ; %end
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; GFX10-WAVE64-NEXT: s_endpgm
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; GFX10-WAVE64-NEXT: .LBB17_6:
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; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
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; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
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; GFX10-WAVE64-NEXT: s_endpgm
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;
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; GFX10-WAVE32-LABEL: scc_use_after_kill_inst:
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; GFX10-WAVE32: ; %bb.0: ; %bb
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; GFX10-WAVE32-NEXT: v_add_f32_e64 v1, s0, 1.0
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; GFX10-WAVE32-NEXT: s_mov_b32 s2, exec_lo
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; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s1, 0
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; GFX10-WAVE32-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
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; GFX10-WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
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; GFX10-WAVE32-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0, v1
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; GFX10-WAVE32-NEXT: s_andn2_b32 s2, s2, vcc_lo
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; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB17_6
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; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb
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; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo
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; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB17_3
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; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb8
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; GFX10-WAVE32-NEXT: v_mov_b32_e32 v1, 8
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; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 4.0
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; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v1, off
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; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-WAVE32-NEXT: .LBB17_3: ; %phibb
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; GFX10-WAVE32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
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; GFX10-WAVE32-NEXT: s_cbranch_vccz .LBB17_5
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; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb10
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; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 9
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; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off
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; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-WAVE32-NEXT: .LBB17_5: ; %end
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; GFX10-WAVE32-NEXT: s_endpgm
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; GFX10-WAVE32-NEXT: .LBB17_6:
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; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0
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; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm
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; GFX10-WAVE32-NEXT: s_endpgm
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;
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; GFX11-LABEL: scc_use_after_kill_inst:
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; GFX11: ; %bb.0: ; %bb
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; GFX11-NEXT: v_add_f32_e64 v1, s0, 1.0
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; GFX11-NEXT: s_mov_b64 s[2:3], exec
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; GFX11-NEXT: s_cmp_lg_u32 s1, 0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
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; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
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; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1
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; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], vcc
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; GFX11-NEXT: s_cbranch_scc0 .LBB17_6
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; GFX11-NEXT: ; %bb.1: ; %bb
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; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc
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; GFX11-NEXT: s_cbranch_scc0 .LBB17_3
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; GFX11-NEXT: ; %bb.2: ; %bb8
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; GFX11-NEXT: v_mov_b32_e32 v1, 8
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; GFX11-NEXT: v_mov_b32_e32 v0, 4.0
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; GFX11-NEXT: global_store_b32 v[0:1], v1, off dlc
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: .LBB17_3: ; %phibb
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; GFX11-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
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; GFX11-NEXT: s_cbranch_vccz .LBB17_5
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; GFX11-NEXT: ; %bb.4: ; %bb10
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; GFX11-NEXT: v_mov_b32_e32 v0, 9
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; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: .LBB17_5: ; %end
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; GFX11-NEXT: s_endpgm
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; GFX11-NEXT: .LBB17_6:
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; GFX11-NEXT: s_mov_b64 exec, 0
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; GFX11-NEXT: exp mrt0 off, off, off, off done
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; GFX11-NEXT: s_endpgm
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bb:
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%tmp = fadd float %x, 1.000000e+00
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%tmp1 = fcmp olt float 0.000000e+00, %tmp
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%tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00
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%cmp.tmp2 = fcmp olt float %tmp2, 0.000000e+00
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%uniform.cond = icmp eq i32 %y, 0
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call void @llvm.amdgcn.kill(i1 %cmp.tmp2)
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br i1 %uniform.cond, label %phibb, label %bb8
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phibb: ; preds = %bb8, %bb
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%tmp5 = phi float [ %tmp2, %bb ], [ 4.000000e+00, %bb8 ]
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%tmp6 = fcmp oeq float %tmp5, 0.000000e+00
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br i1 %tmp6, label %bb10, label %end
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bb8: ; preds = %bb
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store volatile i32 8, ptr addrspace(1) poison, align 4
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br label %phibb
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bb10: ; preds = %phibb
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store volatile i32 9, ptr addrspace(1) poison, align 4
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br label %end
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end: ; preds = %bb10, %phibb
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ret void
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}
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declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #3
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declare float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
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declare <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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