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[PowerPC] Simplify PPCMCExpr::evaluateAsRelocatableImpl

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The signedness of the @l result is dependent on the instruction operand
(gas behavior).
E.g. in `addis 3,3,65535@l`, 65535@l is signed. Unfortunately
we don't have the information.

bfef1dd694 (2014) checked `Fixup`,
which was unnecessary and mislead https://reviews.llvm.org/D115419
to make the code more complex.

In PPCMCExpr::evaluateAsRelocatableImpl we don't need to validate the
result. Just continue and rely on the validation in ELFObjectWriter.
This commit is contained in:
Fangrui Song
2025-03-15 12:45:18 -07:00
parent fc6fd6a2f1
commit 8560da28c6
1 changed files with 6 additions and 14 deletions
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20
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp
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@@ -73,25 +73,17 @@ std::optional<int64_t> PPCMCExpr::evaluateAsInt64(int64_t Value) const {
bool PPCMCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm,
const MCFixup *Fixup) const {
if (!Asm)
return false;
if (!getSubExpr()->evaluateAsRelocatable(Res, Asm, Fixup))
return false;
// The signedness of the result is dependent on the instruction operand. E.g.
// in addis 3,3,65535@l, 65535@l is signed. In the absence of information at
// parse time (!Asm), disable the folding.
std::optional<int64_t> MaybeInt = evaluateAsInt64(Res.getConstant());
if (Res.isAbsolute() && MaybeInt) {
int64_t Result = *MaybeInt;
bool IsHalf16 = Fixup && Fixup->getTargetKind() == PPC::fixup_ppc_half16;
bool IsHalf16DS =
Fixup && Fixup->getTargetKind() == PPC::fixup_ppc_half16ds;
bool IsHalf16DQ =
Fixup && Fixup->getTargetKind() == PPC::fixup_ppc_half16dq;
bool IsHalf = IsHalf16 || IsHalf16DS || IsHalf16DQ;
if (!IsHalf && Result >= 0x8000)
return false;
if ((IsHalf16DS && (Result & 0x3)) || (IsHalf16DQ && (Result & 0xf)))
return false;
Res = MCValue::get(Result);
Res = MCValue::get(*MaybeInt);
} else {
Res = MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(),
getKind());