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[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320)

Browse Source 
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler. The instructions are similar to
`Zvfbfmin` and the only difference with `Zvfbfmin` is that
`XAndesVBFHCvt` doesn't have mask variant.
This commit is contained in:
Jim Lin
2025-06-18 09:17:46 +08:00
committed by GitHub
parent 9265b1f0cf
commit 8ddada41df
11 changed files with 88 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
clang/test/Driver/print-supported-extensions-riscv.c
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@@ -159,6 +159,7 @@
// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-NEXT: xandesvbfhcvt 5.0 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)
// CHECK-NEXT: xandesvdot 5.0 'XAndesVDot' (Andes Vector Dot Product Extension)
// CHECK-NEXT: xandesvpackfph 5.0 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)
// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)

8
clang/test/Preprocessor/riscv-target-features-andes.c
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@@ -15,6 +15,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESPERF %s
// CHECK-XANDESPERF: __riscv_xandesperf 5000000{{$}}
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_xandesvbfhcvt -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64i_xandesvbfhcvt -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s
// CHECK-XANDESVBFHCVT: __riscv_xandesvbfhcvt 5000000{{$}}
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_xandesvpackfph -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVPACKFPH %s

3
llvm/docs/RISCVUsage.rst
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@@ -513,6 +513,9 @@ The current vendor extensions supported are:
``XAndesPerf``
LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
``XAndesVBFHCvt``
LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
``XAndesVPackFPH``
LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.

1
llvm/docs/ReleaseNotes.md
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@@ -210,6 +210,7 @@ Changes to the RISC-V Backend
* The `Shlcofideleg` extension was added.
* `-mcpu=sifive-x390` was added.
* `-mtune=andes-45-series` was added.
* Adds assembler support for the Andes `XAndesvbfhcvt` (Andes Vector BFLOAT16 Conversion extension).
Changes to the WebAssembly Backend
----------------------------------

4
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
View File

@@ -774,8 +774,8 @@ static constexpr FeatureBitset XTHeadGroup = {
RISCV::FeatureVendorXTHeadVdot};
static constexpr FeatureBitset XAndesGroup = {
RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVPackFPH,
RISCV::FeatureVendorXAndesVDot};
RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVBFHCvt,
RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot};
static constexpr DecoderListEntry DecoderList32[]{
// Vendor Extensions

9
llvm/lib/Target/RISCV/RISCVFeatures.td
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@@ -1599,6 +1599,15 @@ def HasVendorXAndesPerf
AssemblerPredicate<(all_of FeatureVendorXAndesPerf),
"'XAndesPerf' (Andes Performance Extension)">;
def FeatureVendorXAndesVBFHCvt
: RISCVExtension<5, 0, "Andes Vector BFLOAT16 Conversion Extension",
[FeatureStdExtZve32f]>;
def HasVendorXAndesVBFHCvt
: Predicate<"Subtarget->hasVendorXAndesVBFHCvt()">,
AssemblerPredicate<(all_of FeatureVendorXAndesVBFHCvt),
"'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)">;
def FeatureVendorXAndesVPackFPH
: RISCVExtension<5, 0, "Andes Vector Packed FP16 Extension",
[FeatureStdExtZvfhmin]>;

31
llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
View File

@@ -361,6 +361,25 @@ class NDSRVInstVD4DOT<bits<6> funct6, string opcodestr>
let RVVConstraint = VMConstraint;
}
class NDSRVInstVBFHCvt<bits<7> funct7, bits<5> vs1, string opcodestr>
: RVInst<(outs VR:$vd), (ins VR:$vs2, VMaskOp:$vm),
opcodestr, "$vd, $vs2", [], InstFormatR> {
bits<5> vs2;
bits<5> vd;
let Inst{31-25} = funct7;
let Inst{24-20} = vs2;
let Inst{19-15} = vs1;
let Inst{14-12} = 0b100;
let Inst{11-7} = vd;
let Inst{6-0} = OPC_CUSTOM_2.Value;
let hasSideEffects = 0;
let mayLoad = 0;
let mayStore = 0;
let Uses = [VL, VTYPE];
}
//===----------------------------------------------------------------------===//
// Multiclass
//===----------------------------------------------------------------------===//
@@ -460,6 +479,18 @@ def NDS_LDGP : NDSRVInstLDGP<0b011, "nds.ldgp">;
def NDS_SDGP : NDSRVInstSDGP<0b111, "nds.sdgp">;
} // Predicates = [HasVendorXAndesPerf, IsRV64]
//===----------------------------------------------------------------------===//
// XAndesVBFHCvt
//===----------------------------------------------------------------------===//
let Predicates = [HasVendorXAndesVBFHCvt], Constraints = "@earlyclobber $vd",
mayRaiseFPException = true in {
let RVVConstraint = VS2Constraint, DestEEW = EEWSEWx2 in
def NDS_VFWCVT_S_BF16 : NDSRVInstVBFHCvt<0b0000000, 0b00000, "nds.vfwcvt.s.bf16">;
let Uses = [FRM, VL, VTYPE] in
def NDS_VFNCVT_BF16_S : NDSRVInstVBFHCvt<0b0000000, 0b00001, "nds.vfncvt.bf16.s">;
}
//===----------------------------------------------------------------------===//
// XAndesVPackFPH
//===----------------------------------------------------------------------===//

4
llvm/test/CodeGen/RISCV/attributes.ll
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@@ -106,6 +106,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s
; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s
; RUN: llc -mtriple=riscv32 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESVBFHCVT %s
; RUN: llc -mtriple=riscv32 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV32XANDESVDOT %s
; RUN: llc -mtriple=riscv32 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV32XANDESVPACKFPH %s
; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
@@ -260,6 +261,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV64XTHEADSYNC %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s
; RUN: llc -mtriple=riscv64 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESVBFHCVT %s
; RUN: llc -mtriple=riscv64 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV64XANDESVDOT %s
; RUN: llc -mtriple=riscv64 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV64XANDESVPACKFPH %s
; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s
@@ -457,6 +459,7 @@
; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p3"
; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0"
; RV32XANDESVBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
; RV32XANDESVDOT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
; RV32XANDESVPACKFPH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0"
; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
@@ -612,6 +615,7 @@
; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0"
; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0"
; RV64XANDESVBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
; RV64XANDESVDOT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
; RV64XANDESVPACKFPH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0"
; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0"

1
llvm/test/CodeGen/RISCV/features-info.ll
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@@ -174,6 +174,7 @@
; CHECK-NEXT: ventana-veyron - Ventana Veyron-Series processors.
; CHECK-NEXT: vxrm-pipeline-flush - VXRM writes causes pipeline flush.
; CHECK-NEXT: xandesperf - 'XAndesPerf' (Andes Performance Extension).
; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension).
; CHECK-NEXT: xandesvdot - 'XAndesVDot' (Andes Vector Dot Product Extension).
; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension).
; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations).

27
llvm/test/MC/RISCV/xandesvbfhcvt-valid.s Normal file
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@@ -0,0 +1,27 @@
# XAndesVBFHCvt - Andes Vector BFLOAT16 Conversion Extension
# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvbfhcvt -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvbfhcvt < %s \
# RUN: | llvm-objdump --mattr=+xandesvbfhcvt -M no-aliases -d -r - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvbfhcvt -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvbfhcvt < %s \
# RUN: | llvm-objdump --mattr=+xandesvbfhcvt -M no-aliases -d -r - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# CHECK-OBJ: nds.vfwcvt.s.bf16 v8, v10
# CHECK-ASM: nds.vfwcvt.s.bf16 v8, v10
# CHECK-ASM: encoding: [0x5b,0x44,0xa0,0x00]
# CHECK-ERROR: instruction requires the following: 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension){{$}}
nds.vfwcvt.s.bf16 v8, v10
# CHECK-OBJ: nds.vfncvt.bf16.s v8, v10
# CHECK-ASM: nds.vfncvt.bf16.s v8, v10
# CHECK-ASM: encoding: [0x5b,0xc4,0xa0,0x00]
# CHECK-ERROR: instruction requires the following: 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension){{$}}
nds.vfncvt.bf16.s v8, v10

1
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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@@ -1130,6 +1130,7 @@ R"(All available -march extensions for RISC-V
svpbmt 1.0
svvptc 1.0
xandesperf 5.0
xandesvbfhcvt 5.0
xandesvdot 5.0
xandesvpackfph 5.0
xcvalu 1.0