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[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320)

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The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only supports assembler. The instructions are similar to
`Zvfbfmin` and the only difference with `Zvfbfmin` is that
`XAndesVBFHCvt` doesn't have mask variant.
This commit is contained in:
Jim Lin
2025-06-18 09:17:46 +08:00
committed by GitHub
parent 9265b1f0cf
commit 8ddada41df
11 changed files with 88 additions and 2 deletions
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3
llvm/docs/RISCVUsage.rst
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@@ -513,6 +513,9 @@ The current vendor extensions supported are:
``XAndesPerf``
LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
``XAndesVBFHCvt``
LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
``XAndesVPackFPH``
LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.

1
llvm/docs/ReleaseNotes.md
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@@ -210,6 +210,7 @@ Changes to the RISC-V Backend
* The `Shlcofideleg` extension was added.
* `-mcpu=sifive-x390` was added.
* `-mtune=andes-45-series` was added.
* Adds assembler support for the Andes `XAndesvbfhcvt` (Andes Vector BFLOAT16 Conversion extension).
Changes to the WebAssembly Backend
----------------------------------