[WebAssembly] Fix inline assembly with vector types (#146574)
This commit fixes using inline assembly with v128 results. Previously this failed with an internal assertion about a failure to legalize a `CopyFromReg` where the source register was typed `v8f16`. It looks like the type used for the destination register was whatever was listed first in the `def V128 : WebAssemblyRegClass` listing, so the types were shuffled around to have a default-supported type. A small test was added as well which failed to generate previously and should now pass in generation. This test passed on LLVM 18 additionally and regressed by accident in #93228 which was first included in LLVM 19.
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@@ -64,8 +64,8 @@ def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>;
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def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
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def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
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def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
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def V128 : WebAssemblyRegClass<[v8f16, v4f32, v2f64, v2i64, v4i32, v16i8,
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v8i16],
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def V128 : WebAssemblyRegClass<[v2i64, v4i32, v16i8, v8i16,
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v8f16, v4f32, v2f64],
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128, (add V128_0)>;
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def FUNCREF : WebAssemblyRegClass<[funcref], 0, (add FUNCREF_0)>;
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def EXTERNREF : WebAssemblyRegClass<[externref], 0, (add EXTERNREF_0)>;
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@@ -129,7 +129,18 @@ entry:
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ret i32 %ret
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}
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; CHECK-LABEL: v128_load
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; CHECK: local.get 0
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; CHECK-NEXT: v128.load 0
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; CHECK-NEXT: local.set 1
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define <4 x i32> @v128_load(ptr %v) #1 {
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entry:
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%0 = tail call <4 x i32> asm "local.get $1\0Av128.load 0\0Alocal.set $0", "=r,r"(ptr %v)
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ret <4 x i32> %0
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}
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attributes #0 = { nounwind }
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attributes #1 = { "target-features"="+simd128" }
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!0 = !{i32 47}
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!1 = !{i32 145}
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