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Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)

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Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html,
https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this
PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine`
interface classes. More specifically:
1. Makes `TargetMachine` the only class implemented under
`TargetMachine.h` in the `Target` library.
2. `TargetMachine` contains target-specific interface functions that
relate to IR/CodeGen/MC constructs, whereas before (at least on paper)
it was supposed to have only IR/MC constructs. Any Target that doesn't
want to use the independent code generator simply does not implement
them, and returns either `false` or `nullptr`.
3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming
aims to make the purpose of `LLVMTargetMachine` clearer. Its interface
was moved under the CodeGen library, to further emphasis its usage in
Targets that use CodeGen directly.
4. Makes `TargetMachine` the only interface used across LLVM and its
projects. With these changes, `CodeGenCommonTMImpl` is simply a set of
shared function implementations of `TargetMachine`, and CodeGen users
don't need to static cast to `LLVMTargetMachine` every time they need a
CodeGen-specific feature of the `TargetMachine`.
5. More importantly, does not change any requirements regarding library
linking.

cc @arsenm @aeubanks
This commit is contained in:
Matin Raayai
2024-11-14 21:30:05 +00:00
committed by GitHub
parent 5d16fbc275
commit bb3f5e1fed
122 changed files with 507 additions and 485 deletions
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18
llvm/docs/WritingAnLLVMBackend.rst
View File

@@ -152,7 +152,7 @@ To make your target actually do something, you need to implement a subclass of
``lib/Target/DummyTargetMachine.cpp``, but any file in the ``lib/Target``
directory will be built and should work. To use LLVM's target independent code
generator, you should do what all current machine backends do: create a
subclass of ``LLVMTargetMachine``. (To create a target from scratch, create a
subclass of ``CodeGenTargetMachineImpl``. (To create a target from scratch, create a
subclass of ``TargetMachine``.)
To get LLVM to actually build and link your target, you need to run ``cmake``
@@ -165,15 +165,15 @@ located in the main ``CMakeLists.txt``.
Target Machine
==============
``LLVMTargetMachine`` is designed as a base class for targets implemented with
the LLVM target-independent code generator. The ``LLVMTargetMachine`` class
``CodeGenTargetMachineImpl`` is designed as a base class for targets implemented with
the LLVM target-independent code generator. The ``CodeGenTargetMachineImpl`` class
should be specialized by a concrete target class that implements the various
virtual methods. ``LLVMTargetMachine`` is defined as a subclass of
``TargetMachine`` in ``include/llvm/Target/TargetMachine.h``. The
``TargetMachine`` class implementation (``TargetMachine.cpp``) also processes
numerous command-line options.
virtual methods. ``CodeGenTargetMachineImpl`` is defined as a subclass of
``TargetMachine`` in ``include/llvm/CodeGen/CodeGenTargetMachineImpl.h``. The
``TargetMachine`` class implementation (``include/llvm/Target/TargetMachine.cpp``)
also processes numerous command-line options.
To create a concrete target-specific subclass of ``LLVMTargetMachine``, start
To create a concrete target-specific subclass of ``CodeGenTargetMachineImpl``, start
by copying an existing ``TargetMachine`` class and header. You should name the
files that you create to reflect your specific target. For instance, for the
SPARC target, name the files ``SparcTargetMachine.h`` and
@@ -197,7 +197,7 @@ simply return a class member.
class Module;
class SparcTargetMachine : public LLVMTargetMachine {
class SparcTargetMachine : public CodeGenTargetMachineImpl {
const DataLayout DataLayout; // Calculates type size & alignment
SparcSubtarget Subtarget;
SparcInstrInfo InstrInfo;

95
llvm/include/llvm/CodeGen/CodeGenTargetMachineImpl.h Normal file
View File

@@ -0,0 +1,95 @@
//===-- CodeGenTargetMachineImpl.h ------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file This file describes the CodeGenTargetMachineImpl class, which
/// implements a set of functionality used by \c TargetMachine classes in
/// LLVM that make use of the target-independent code generator.
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_CODEGENTARGETMACHINEIMPL_H
#define LLVM_CODEGEN_CODEGENTARGETMACHINEIMPL_H
#include "llvm/Target/TargetMachine.h"
namespace llvm {
/// \brief implements a set of functionality in the \c TargetMachine class
/// for targets that make use of the independent code generator (CodeGen)
/// library. Must not be used directly in code unless to inherit its
/// implementation.
class CodeGenTargetMachineImpl : public TargetMachine {
protected: // Can only create subclasses.
CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString,
const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOptLevel OL);
void initAsmInfo();
/// Reset internal state.
virtual void reset() {};
public:
/// Get a TargetTransformInfo implementation for the target.
///
/// The TTI returned uses the common code generator to answer queries about
/// the IR.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
/// Create a pass configuration object to be used by addPassToEmitX methods
/// for generating a pipeline of CodeGen passes.
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
/// Add passes to the specified pass manager to get the specified file
/// emitted. Typically this will involve several steps of code generation.
/// \p MMIWP is an optional parameter that, if set to non-nullptr,
/// will be used to set the MachineModuloInfo for this PM.
bool
addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
bool DisableVerify = true,
MachineModuleInfoWrapperPass *MMIWP = nullptr) override;
/// Add passes to the specified pass manager to get machine code emitted with
/// the MCJIT. This method returns true if machine code is not supported. It
/// fills the MCContext Ctx pointer which can be used to build custom
/// MCStreamer.
bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
raw_pwrite_stream &Out,
bool DisableVerify = true) override;
/// Adds an AsmPrinter pass to the pipeline that prints assembly or
/// machine code from the MI representation.
bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
MCContext &Context) override;
Expected<std::unique_ptr<MCStreamer>>
createMCStreamer(raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
CodeGenFileType FileType, MCContext &Ctx) override;
};
/// Helper method for getting the code model, returning Default if
/// CM does not have a value. The tiny and kernel models will produce
/// an error, so targets that support them or require more complex codemodel
/// selection logic should implement and call their own getEffectiveCodeModel.
inline CodeModel::Model
getEffectiveCodeModel(std::optional<CodeModel::Model> CM,
CodeModel::Model Default) {
if (CM) {
// By default, targets do not support the tiny and kernel models.
if (*CM == CodeModel::Tiny)
report_fatal_error("Target does not support the tiny CodeModel", false);
if (*CM == CodeModel::Kernel)
report_fatal_error("Target does not support the kernel CodeModel", false);
return *CM;
}
return Default;
}
} // namespace llvm
#endif

8
llvm/include/llvm/CodeGen/MachineFunction.h
View File

@@ -54,7 +54,7 @@ class DILocation;
class Function;
class GISelChangeObserver;
class GlobalValue;
class LLVMTargetMachine;
class TargetMachine;
class MachineConstantPool;
class MachineFrameInfo;
class MachineFunction;
@@ -256,7 +256,7 @@ struct LandingPadInfo {
class LLVM_ABI MachineFunction {
Function &F;
const LLVMTargetMachine &Target;
const TargetMachine &Target;
const TargetSubtargetInfo *STI;
MCContext &Ctx;
@@ -633,7 +633,7 @@ public:
/// for instructions that have a stack spill fused into them.
const static unsigned int DebugOperandMemNumber;
MachineFunction(Function &F, const LLVMTargetMachine &Target,
MachineFunction(Function &F, const TargetMachine &Target,
const TargetSubtargetInfo &STI, MCContext &Ctx,
unsigned FunctionNum);
MachineFunction(const MachineFunction &) = delete;
@@ -706,7 +706,7 @@ public:
void assignBeginEndSections();
/// getTarget - Return the target machine this machine code is compiled with
const LLVMTargetMachine &getTarget() const { return Target; }
const TargetMachine &getTarget() const { return Target; }
/// getSubtarget - Return the subtarget for which this machine code is being
/// compiled.

6
llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h
View File

@@ -18,7 +18,7 @@
namespace llvm {
class MachineFunction;
class LLVMTargetMachine;
class TargetMachine;
/// This analysis create MachineFunction for given Function.
/// To release the MachineFunction, users should invalidate it explicitly.
@@ -28,7 +28,7 @@ class MachineFunctionAnalysis
static AnalysisKey Key;
const LLVMTargetMachine *TM;
const TargetMachine *TM;
public:
class Result {
@@ -41,7 +41,7 @@ public:
FunctionAnalysisManager::Invalidator &);
};
MachineFunctionAnalysis(const LLVMTargetMachine *TM) : TM(TM){};
MachineFunctionAnalysis(const TargetMachine *TM) : TM(TM) {};
Result run(Function &F, FunctionAnalysisManager &FAM);
};

15
llvm/include/llvm/CodeGen/MachineModuleInfo.h
View File

@@ -43,7 +43,7 @@
namespace llvm {
class Function;
class LLVMTargetMachine;
class TargetMachine;
class MachineFunction;
class Module;
@@ -83,7 +83,7 @@ class MachineModuleInfo {
friend class MachineModuleInfoWrapperPass;
friend class MachineModuleAnalysis;
const LLVMTargetMachine &TM;
const TargetMachine &TM;
/// This is the MCContext used for the entire code generator.
MCContext Context;
@@ -109,10 +109,9 @@ class MachineModuleInfo {
MachineModuleInfo &operator=(MachineModuleInfo &&MMII) = delete;
public:
explicit MachineModuleInfo(const LLVMTargetMachine *TM = nullptr);
explicit MachineModuleInfo(const TargetMachine *TM = nullptr);
explicit MachineModuleInfo(const LLVMTargetMachine *TM,
MCContext *ExtContext);
explicit MachineModuleInfo(const TargetMachine *TM, MCContext *ExtContext);
MachineModuleInfo(MachineModuleInfo &&MMII);
@@ -121,7 +120,7 @@ public:
void initialize();
void finalize();
const LLVMTargetMachine &getTarget() const { return TM; }
const TargetMachine &getTarget() const { return TM; }
const MCContext &getContext() const {
return ExternalContext ? *ExternalContext : Context;
@@ -173,9 +172,9 @@ class MachineModuleInfoWrapperPass : public ImmutablePass {
public:
static char ID; // Pass identification, replacement for typeid
explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM = nullptr);
explicit MachineModuleInfoWrapperPass(const TargetMachine *TM = nullptr);
explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM,
explicit MachineModuleInfoWrapperPass(const TargetMachine *TM,
MCContext *ExtContext);
// Initialization and Finalization

6
llvm/include/llvm/CodeGen/RegisterUsageInfo.h
View File

@@ -29,7 +29,7 @@
namespace llvm {
class Function;
class LLVMTargetMachine;
class TargetMachine;
class PhysicalRegisterUsageInfo : public ImmutablePass {
public:
@@ -41,7 +41,7 @@ public:
}
/// Set TargetMachine which is used to print analysis.
void setTargetMachine(const LLVMTargetMachine &TM);
void setTargetMachine(const TargetMachine &TM);
bool doInitialization(Module &M) override;
@@ -63,7 +63,7 @@ private:
/// and 1 means content of register will be preserved around function call.
DenseMap<const Function *, std::vector<uint32_t>> RegMasks;
const LLVMTargetMachine *TM = nullptr;
const TargetMachine *TM = nullptr;
};
} // end namespace llvm

4
llvm/include/llvm/CodeGen/ScheduleDAG.h
View File

@@ -32,7 +32,7 @@ namespace llvm {
template <class GraphType> struct GraphTraits;
template<class Graph> class GraphWriter;
class LLVMTargetMachine;
class TargetMachine;
class MachineFunction;
class MachineRegisterInfo;
class MCInstrDesc;
@@ -571,7 +571,7 @@ class TargetRegisterInfo;
class ScheduleDAG {
public:
const LLVMTargetMachine &TM; ///< Target processor
const TargetMachine &TM; ///< Target processor
const TargetInstrInfo *TII; ///< Target instruction information
const TargetRegisterInfo *TRI; ///< Target processor register info
MachineFunction &MF; ///< Machine function

10
llvm/include/llvm/CodeGen/TargetPassConfig.h
View File

@@ -21,7 +21,7 @@
namespace llvm {
class LLVMTargetMachine;
class TargetMachine;
struct MachineSchedContext;
class PassConfigImpl;
class ScheduleDAGInstrs;
@@ -120,7 +120,7 @@ private:
void setStartStopPasses();
protected:
LLVMTargetMachine *TM;
TargetMachine *TM;
PassConfigImpl *Impl = nullptr; // Internal data structures
bool Initialized = false; // Flagged after all passes are configured.
@@ -148,7 +148,7 @@ protected:
bool addCoreISelPasses();
public:
TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm);
TargetPassConfig(TargetMachine &TM, PassManagerBase &PM);
// Dummy constructor.
TargetPassConfig();
@@ -413,7 +413,7 @@ protected:
virtual void addFastRegAlloc();
/// addOptimizedRegAlloc - Add passes related to register allocation.
/// LLVMTargetMachine provides standard regalloc passes for most targets.
/// CodeGenCommonTMImpl provides standard regalloc passes for most targets.
virtual void addOptimizedRegAlloc();
/// addPreRewrite - Add passes to the optimized register allocation pipeline
@@ -497,7 +497,7 @@ protected:
};
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
LLVMTargetMachine &);
TargetMachine &);
} // end namespace llvm

2
llvm/include/llvm/Passes/CodeGenPassBuilder.h
View File

@@ -443,7 +443,7 @@ protected:
Error addFastRegAlloc(AddMachinePass &) const;
/// addOptimizedRegAlloc - Add passes related to register allocation.
/// LLVMTargetMachine provides standard regalloc passes for most targets.
/// CodeGenCommonTMImpl provides standard regalloc passes for most targets.
void addOptimizedRegAlloc(AddMachinePass &) const;
/// Add passes that optimize machine instructions after register allocation.

93
llvm/include/llvm/Target/TargetMachine.h
View File

@@ -5,9 +5,9 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines the TargetMachine and LLVMTargetMachine classes.
//
///
/// This file defines the TargetMachine class.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_TARGETMACHINE_H
@@ -16,6 +16,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/PassManager.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Error.h"
@@ -40,7 +41,6 @@ class MCAsmInfo;
class MCContext;
class MCInstrInfo;
class MCRegisterInfo;
class MCStreamer;
class MCSubtargetInfo;
class MCSymbol;
class raw_pwrite_stream;
@@ -60,13 +60,13 @@ class TargetSubtargetInfo;
// The old pass manager infrastructure is hidden in a legacy namespace now.
namespace legacy {
class PassManagerBase;
}
} // namespace legacy
using legacy::PassManagerBase;
struct MachineFunctionInfo;
namespace yaml {
struct MachineFunctionInfo;
}
} // namespace yaml
//===----------------------------------------------------------------------===//
///
@@ -434,43 +434,12 @@ public:
function_ref<void(std::unique_ptr<Module> MPart)> ModuleCallback) {
return false;
}
};
/// This class describes a target machine that is implemented with the LLVM
/// target-independent code generator.
///
class LLVMTargetMachine : public TargetMachine {
protected: // Can only create subclasses.
LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOptLevel OL);
void initAsmInfo();
/// Reset internal state.
virtual void reset() {};
public:
/// Get a TargetTransformInfo implementation for the target.
///
/// The TTI returned uses the common code generator to answer queries about
/// the IR.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
/// Create a pass configuration object to be used by addPassToEmitX methods
/// for generating a pipeline of CodeGen passes.
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
/// Add passes to the specified pass manager to get the specified file
/// emitted. Typically this will involve several steps of code generation.
/// \p MMIWP is an optional parameter that, if set to non-nullptr,
/// will be used to set the MachineModuloInfo for this PM.
bool
addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
bool DisableVerify = true,
MachineModuleInfoWrapperPass *MMIWP = nullptr) override;
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM) {
return nullptr;
}
virtual Error buildCodeGenPipeline(ModulePassManager &, raw_pwrite_stream &,
raw_pwrite_stream *, CodeGenFileType,
@@ -480,14 +449,6 @@ public:
inconvertibleErrorCode());
}
/// Add passes to the specified pass manager to get machine code emitted with
/// the MCJIT. This method returns true if machine code is not supported. It
/// fills the MCContext Ctx pointer which can be used to build custom
/// MCStreamer.
bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
raw_pwrite_stream &Out,
bool DisableVerify = true) override;
/// Returns true if the target is expected to pass all machine verifier
/// checks. This is a stopgap measure to fix targets one by one. We will
/// remove this at some point and always enable the verifier when
@@ -496,13 +457,17 @@ public:
/// Adds an AsmPrinter pass to the pipeline that prints assembly or
/// machine code from the MI representation.
bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
MCContext &Context);
virtual bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut,
CodeGenFileType FileType, MCContext &Context) {
return false;
}
Expected<std::unique_ptr<MCStreamer>>
virtual Expected<std::unique_ptr<MCStreamer>>
createMCStreamer(raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
CodeGenFileType FileType, MCContext &Ctx);
CodeGenFileType FileType, MCContext &Ctx) {
return nullptr;
}
/// True if the target uses physical regs (as nearly all targets do). False
/// for stack machines such as WebAssembly and other virtual-register
@@ -514,9 +479,7 @@ public:
/// True if the target wants to use interprocedural register allocation by
/// default. The -enable-ipra flag can be used to override this.
virtual bool useIPRA() const {
return false;
}
virtual bool useIPRA() const { return false; }
/// The default variant to use in unqualified `asm` instructions.
/// If this returns 0, `asm "$(foo$|bar$)"` will evaluate to `asm "foo"`.
@@ -526,24 +489,6 @@ public:
virtual void registerMachineRegisterInfoCallback(MachineFunction &MF) const {}
};
/// Helper method for getting the code model, returning Default if
/// CM does not have a value. The tiny and kernel models will produce
/// an error, so targets that support them or require more complex codemodel
/// selection logic should implement and call their own getEffectiveCodeModel.
inline CodeModel::Model
getEffectiveCodeModel(std::optional<CodeModel::Model> CM,
CodeModel::Model Default) {
if (CM) {
// By default, targets do not support the tiny and kernel models.
if (*CM == CodeModel::Tiny)
report_fatal_error("Target does not support the tiny CodeModel", false);
if (*CM == CodeModel::Kernel)
report_fatal_error("Target does not support the kernel CodeModel", false);
return *CM;
}
return Default;
}
} // end namespace llvm
#endif // LLVM_TARGET_TARGETMACHINE_H

2
llvm/lib/CodeGen/CMakeLists.txt
View File

@@ -100,7 +100,7 @@ add_llvm_component_library(LLVMCodeGen
LiveRegUnits.cpp
LiveStacks.cpp
LiveVariables.cpp
LLVMTargetMachine.cpp
CodeGenTargetMachineImpl.cpp
LocalStackSlotAllocation.cpp
LoopTraversal.cpp
LowLevelTypeUtils.cpp

57
llvm/lib/CodeGen/LLVMTargetMachine.cpp → llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
View File

@@ -1,16 +1,16 @@
//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
//===-- CodeGenTargetMachineImpl.cpp --------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements the LLVMTargetMachine class.
//
///
/// \file This file implements the CodeGenTargetMachineImpl class.
///
//===----------------------------------------------------------------------===//
#include "llvm/Analysis/Passes.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
@@ -42,7 +42,7 @@ static cl::opt<bool> EnableNoTrapAfterNoreturn(
cl::desc("Do not emit a trap instruction for 'unreachable' IR instructions "
"after noreturn calls, even if --trap-unreachable is set."));
void LLVMTargetMachine::initAsmInfo() {
void CodeGenTargetMachineImpl::initAsmInfo() {
MRI.reset(TheTarget.createMCRegInfo(getTargetTriple().str()));
assert(MRI && "Unable to create reg info");
MII.reset(TheTarget.createMCInstrInfo());
@@ -62,8 +62,8 @@ void LLVMTargetMachine::initAsmInfo() {
// we'll crash later.
// Provide the user with a useful error message about what's wrong.
assert(TmpAsmInfo && "MCAsmInfo not initialized. "
"Make sure you include the correct TargetSelect.h"
"and that InitializeAllTargetMCs() is being invoked!");
"Make sure you include the correct TargetSelect.h"
"and that InitializeAllTargetMCs() is being invoked!");
if (Options.BinutilsVersion.first > 0)
TmpAsmInfo->setBinutilsVersion(Options.BinutilsVersion);
@@ -85,12 +85,10 @@ void LLVMTargetMachine::initAsmInfo() {
AsmInfo.reset(TmpAsmInfo);
}
LLVMTargetMachine::LLVMTargetMachine(const Target &T,
StringRef DataLayoutString,
const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOptLevel OL)
CodeGenTargetMachineImpl::CodeGenTargetMachineImpl(
const Target &T, StringRef DataLayoutString, const Triple &TT,
StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOptLevel OL)
: TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) {
this->RM = RM;
this->CMModel = CM;
@@ -103,13 +101,13 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T,
}
TargetTransformInfo
LLVMTargetMachine::getTargetTransformInfo(const Function &F) const {
CodeGenTargetMachineImpl::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(BasicTTIImpl(this, F));
}
/// addPassesToX helper drives creation and initialization of TargetPassConfig.
static TargetPassConfig *
addPassesToGenerateCode(LLVMTargetMachine &TM, PassManagerBase &PM,
addPassesToGenerateCode(CodeGenTargetMachineImpl &TM, PassManagerBase &PM,
bool DisableVerify,
MachineModuleInfoWrapperPass &MMIWP) {
// Targets may override createPassConfig to provide a target-specific
@@ -127,11 +125,11 @@ addPassesToGenerateCode(LLVMTargetMachine &TM, PassManagerBase &PM,
return PassConfig;
}
bool LLVMTargetMachine::addAsmPrinter(PassManagerBase &PM,
raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut,
CodeGenFileType FileType,
MCContext &Context) {
bool CodeGenTargetMachineImpl::addAsmPrinter(PassManagerBase &PM,
raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut,
CodeGenFileType FileType,
MCContext &Context) {
Expected<std::unique_ptr<MCStreamer>> MCStreamerOrErr =
createMCStreamer(Out, DwoOut, FileType, Context);
if (auto Err = MCStreamerOrErr.takeError())
@@ -147,9 +145,11 @@ bool LLVMTargetMachine::addAsmPrinter(PassManagerBase &PM,
return false;
}
Expected<std::unique_ptr<MCStreamer>> LLVMTargetMachine::createMCStreamer(
raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
MCContext &Context) {
Expected<std::unique_ptr<MCStreamer>>
CodeGenTargetMachineImpl::createMCStreamer(raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut,
CodeGenFileType FileType,
MCContext &Context) {
const MCSubtargetInfo &STI = *getMCSubtargetInfo();
const MCAsmInfo &MAI = *getMCAsmInfo();
const MCRegisterInfo &MRI = *getMCRegisterInfo();
@@ -208,7 +208,7 @@ Expected<std::unique_ptr<MCStreamer>> LLVMTargetMachine::createMCStreamer(
return std::move(AsmStreamer);
}
bool LLVMTargetMachine::addPassesToEmitFile(
bool CodeGenTargetMachineImpl::addPassesToEmitFile(
PassManagerBase &PM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
CodeGenFileType FileType, bool DisableVerify,
MachineModuleInfoWrapperPass *MMIWP) {
@@ -238,9 +238,10 @@ bool LLVMTargetMachine::addPassesToEmitFile(
/// code is not supported. It fills the MCContext Ctx pointer which can be
/// used to build custom MCStreamer.
///
bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
raw_pwrite_stream &Out,
bool DisableVerify) {
bool CodeGenTargetMachineImpl::addPassesToEmitMC(PassManagerBase &PM,
MCContext *&Ctx,
raw_pwrite_stream &Out,
bool DisableVerify) {
// Add common CodeGen passes.
MachineModuleInfoWrapperPass *MMIWP = new MachineModuleInfoWrapperPass(this);
TargetPassConfig *PassConfig =

6
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
View File

@@ -314,7 +314,7 @@ bool MIRParserImpl::parseMachineFunction(Module &M, MachineModuleInfo &MMI,
yaml::MachineFunction YamlMF;
yaml::EmptyContext Ctx;
const LLVMTargetMachine &TM = MMI.getTarget();
const TargetMachine &TM = MMI.getTarget();
YamlMF.MachineFuncInfo = std::unique_ptr<yaml::MachineFunctionInfo>(
TM.createDefaultFuncInfoYAML());
@@ -461,7 +461,7 @@ bool MIRParserImpl::initializeCallSiteInfo(
PerFunctionMIParsingState &PFS, const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
SMDiagnostic Error;
const LLVMTargetMachine &TM = MF.getTarget();
const TargetMachine &TM = MF.getTarget();
for (auto &YamlCSInfo : YamlMF.CallSitesInfo) {
yaml::CallSiteInfo::MachineInstrLoc MILoc = YamlCSInfo.CallLocation;
if (MILoc.BlockNum >= MF.size())
@@ -615,7 +615,7 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
return true;
if (YamlMF.MachineFuncInfo) {
const LLVMTargetMachine &TM = MF.getTarget();
const TargetMachine &TM = MF.getTarget();
// Note this is called after the initial constructor of the
// MachineFunctionInfo based on the MachineFunction, which may depend on the
// IR.

2
llvm/lib/CodeGen/MachineFunction.cpp
View File

@@ -160,7 +160,7 @@ static inline Align getFnStackAlignment(const TargetSubtargetInfo *STI,
return STI->getFrameLowering()->getStackAlign();
}
MachineFunction::MachineFunction(Function &F, const LLVMTargetMachine &Target,
MachineFunction::MachineFunction(Function &F, const TargetMachine &Target,
const TargetSubtargetInfo &STI, MCContext &Ctx,
unsigned FunctionNum)
: F(F), Target(Target), STI(&STI), Ctx(Ctx) {

8
llvm/lib/CodeGen/MachineModuleInfo.cpp
View File

@@ -48,7 +48,7 @@ MachineModuleInfo::MachineModuleInfo(MachineModuleInfo &&MMI)
TheModule = MMI.TheModule;
}
MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM)
MachineModuleInfo::MachineModuleInfo(const TargetMachine *TM)
: TM(*TM), Context(TM->getTargetTriple(), TM->getMCAsmInfo(),
TM->getMCRegisterInfo(), TM->getMCSubtargetInfo(),
nullptr, &TM->Options.MCOptions, false) {
@@ -56,7 +56,7 @@ MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM)
initialize();
}
MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM,
MachineModuleInfo::MachineModuleInfo(const TargetMachine *TM,
MCContext *ExtContext)
: TM(*TM), Context(TM->getTargetTriple(), TM->getMCAsmInfo(),
TM->getMCRegisterInfo(), TM->getMCSubtargetInfo(),
@@ -151,13 +151,13 @@ FunctionPass *llvm::createFreeMachineFunctionPass() {
}
MachineModuleInfoWrapperPass::MachineModuleInfoWrapperPass(
const LLVMTargetMachine *TM)
const TargetMachine *TM)
: ImmutablePass(ID), MMI(TM) {
initializeMachineModuleInfoWrapperPassPass(*PassRegistry::getPassRegistry());
}
MachineModuleInfoWrapperPass::MachineModuleInfoWrapperPass(
const LLVMTargetMachine *TM, MCContext *ExtContext)
const TargetMachine *TM, MCContext *ExtContext)
: ImmutablePass(ID), MMI(TM, ExtContext) {
initializeMachineModuleInfoWrapperPassPass(*PassRegistry::getPassRegistry());
}

2
llvm/lib/CodeGen/RegUsageInfoCollector.cpp
View File

@@ -100,7 +100,7 @@ static bool isCallableFunction(const MachineFunction &MF) {
bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
MachineRegisterInfo *MRI = &MF.getRegInfo();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const LLVMTargetMachine &TM = MF.getTarget();
const TargetMachine &TM = MF.getTarget();
LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
<< " -------------------- \nFunction Name : "

2
llvm/lib/CodeGen/RegisterUsageInfo.cpp
View File

@@ -37,7 +37,7 @@ INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info",
char PhysicalRegisterUsageInfo::ID = 0;
void PhysicalRegisterUsageInfo::setTargetMachine(const LLVMTargetMachine &TM) {
void PhysicalRegisterUsageInfo::setTargetMachine(const TargetMachine &TM) {
this->TM = &TM;
}

2
llvm/lib/CodeGen/ResetMachineFunctionPass.cpp
View File

@@ -69,7 +69,7 @@ namespace {
MF.reset();
MF.initTargetMachineFunctionInfo(MF.getSubtarget());
const LLVMTargetMachine &TM = MF.getTarget();
const TargetMachine &TM = MF.getTarget();
// MRI callback for target specific initializations.
TM.registerMachineRegisterInfoCallback(MF);

10
llvm/lib/CodeGen/TargetPassConfig.cpp
View File

@@ -22,6 +22,7 @@
#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
#include "llvm/CodeGen/BasicBlockSectionsProfileReader.h"
#include "llvm/CodeGen/CSEConfigBase.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/Passes.h"
@@ -514,7 +515,7 @@ CGPassBuilderOption llvm::getCGPassBuilderOption() {
}
void llvm::registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
LLVMTargetMachine &LLVMTM) {
TargetMachine &TM) {
// Register a callback for disabling passes.
PIC.registerShouldRunOptionalPassCallback([](StringRef P, Any) {
@@ -577,8 +578,8 @@ TargetPassConfig::getStartStopInfo(PassInstrumentationCallbacks &PIC) {
// Out of line constructor provides default values for pass options and
// registers all common codegen passes.
TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
: ImmutablePass(ID), PM(&pm), TM(&TM) {
TargetPassConfig::TargetPassConfig(TargetMachine &TM, PassManagerBase &PM)
: ImmutablePass(ID), PM(&PM), TM(&TM) {
Impl = new PassConfigImpl();
// Register all target independent codegen passes to activate their PassIDs,
@@ -624,7 +625,8 @@ void TargetPassConfig::insertPass(AnalysisID TargetPassID,
/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
///
/// Targets may override this to extend TargetPassConfig.
TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
TargetPassConfig *
CodeGenTargetMachineImpl::createPassConfig(PassManagerBase &PM) {
return new TargetPassConfig(*this, PM);
}

4
llvm/lib/Passes/PassRegistry.def
View File

@@ -284,9 +284,7 @@ FUNCTION_ANALYSIS("demanded-bits", DemandedBitsAnalysis())
FUNCTION_ANALYSIS("domfrontier", DominanceFrontierAnalysis())
FUNCTION_ANALYSIS("domtree", DominatorTreeAnalysis())
FUNCTION_ANALYSIS("func-properties", FunctionPropertiesAnalysis())
FUNCTION_ANALYSIS(
"machine-function-info",
MachineFunctionAnalysis(static_cast<const LLVMTargetMachine *>(TM)))
FUNCTION_ANALYSIS("machine-function-info", MachineFunctionAnalysis(TM))
FUNCTION_ANALYSIS("gc-function", GCFunctionAnalysis())
FUNCTION_ANALYSIS("inliner-size-estimator", InlineSizeEstimatorAnalysis())
FUNCTION_ANALYSIS("last-run-tracking", LastRunTrackingAnalysis())

10
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@@ -357,11 +357,11 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT,
bool LittleEndian)
: LLVMTargetMachine(T,
computeDataLayout(TT, Options.MCOptions, LittleEndian),
TT, computeDefaultCPU(TT, CPU), FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
: CodeGenTargetMachineImpl(
T, computeDataLayout(TT, Options.MCOptions, LittleEndian), TT,
computeDefaultCPU(TT, CPU), FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
initAsmInfo();

4
llvm/lib/Target/AArch64/AArch64TargetMachine.h
View File

@@ -15,13 +15,13 @@
#include "AArch64InstrInfo.h"
#include "AArch64Subtarget.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
#include <optional>
namespace llvm {
class AArch64TargetMachine : public LLVMTargetMachine {
class AArch64TargetMachine : public CodeGenTargetMachineImpl {
protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;

8
llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
View File

@@ -95,7 +95,7 @@ void MCResourceInfo::assignResourceInfoExpr(
int64_t LocalValue, ResourceInfoKind RIK, AMDGPUMCExpr::VariantKind Kind,
const MachineFunction &MF, const SmallVectorImpl<const Function *> &Callees,
MCContext &OutContext) {
const LLVMTargetMachine &TM = MF.getTarget();
const TargetMachine &TM = MF.getTarget();
MCSymbol *FnSym = TM.getSymbol(&MF.getFunction());
const MCConstantExpr *LocalConstExpr =
MCConstantExpr::create(LocalValue, OutContext);
@@ -137,7 +137,7 @@ void MCResourceInfo::gatherResourceInfo(
addMaxSGPRCandidate(FRI.NumExplicitSGPR);
}
const LLVMTargetMachine &TM = MF.getTarget();
const TargetMachine &TM = MF.getTarget();
MCSymbol *FnSym = TM.getSymbol(&MF.getFunction());
auto SetMaxReg = [&](MCSymbol *MaxSym, int32_t numRegs,
@@ -221,7 +221,7 @@ void MCResourceInfo::gatherResourceInfo(
const MCExpr *MCResourceInfo::createTotalNumVGPRs(const MachineFunction &MF,
MCContext &Ctx) {
const LLVMTargetMachine &TM = MF.getTarget();
const TargetMachine &TM = MF.getTarget();
MCSymbol *FnSym = TM.getSymbol(&MF.getFunction());
return AMDGPUMCExpr::createTotalNumVGPR(
getSymRefExpr(FnSym->getName(), RIK_NumAGPR, Ctx),
@@ -231,7 +231,7 @@ const MCExpr *MCResourceInfo::createTotalNumVGPRs(const MachineFunction &MF,
const MCExpr *MCResourceInfo::createTotalNumSGPRs(const MachineFunction &MF,
bool hasXnack,
MCContext &Ctx) {
const LLVMTargetMachine &TM = MF.getTarget();
const TargetMachine &TM = MF.getTarget();
MCSymbol *FnSym = TM.getSymbol(&MF.getFunction());
return MCBinaryExpr::createAdd(
getSymRefExpr(FnSym->getName(), RIK_NumSGPR, Ctx),

13
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View File

@@ -659,9 +659,10 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OptLevel)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
: CodeGenTargetMachineImpl(
T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
TLOF(createTLOF(getTargetTriple())) {
initAsmInfo();
if (TT.getArch() == Triple::amdgcn) {
@@ -1007,8 +1008,8 @@ namespace {
class GCNPassConfig final : public AMDGPUPassConfig {
public:
GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
: AMDGPUPassConfig(TM, PM) {
GCNPassConfig(TargetMachine &TM, PassManagerBase &PM)
: AMDGPUPassConfig(TM, PM) {
// It is necessary to know the register usage of the entire call graph. We
// allow calls without EnableAMDGPUFunctionCalls if they are marked
// noinline, so this is always required.
@@ -1070,7 +1071,7 @@ public:
} // end anonymous namespace
AMDGPUPassConfig::AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
AMDGPUPassConfig::AMDGPUPassConfig(TargetMachine &TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {
// Exceptions and StackMaps are not supported, so these passes will never do
// anything.

6
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
View File

@@ -15,10 +15,10 @@
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
#include "GCNSubtarget.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Passes/CodeGenPassBuilder.h"
#include "llvm/Target/TargetMachine.h"
#include <optional>
#include <utility>
@@ -28,7 +28,7 @@ namespace llvm {
// AMDGPU Target Machine (R600+)
//===----------------------------------------------------------------------===//
class AMDGPUTargetMachine : public LLVMTargetMachine {
class AMDGPUTargetMachine : public CodeGenTargetMachineImpl {
protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
@@ -123,7 +123,7 @@ public:
class AMDGPUPassConfig : public TargetPassConfig {
public:
AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM);
AMDGPUPassConfig(TargetMachine &TM, PassManagerBase &PM);
AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
return getTM<AMDGPUTargetMachine>();

2
llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
View File

@@ -93,7 +93,7 @@ R600TargetMachine::getTargetTransformInfo(const Function &F) const {
namespace {
class R600PassConfig final : public AMDGPUPassConfig {
public:
R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
R600PassConfig(TargetMachine &TM, PassManagerBase &PM)
: AMDGPUPassConfig(TM, PM) {}
ScheduleDAGInstrs *

10
llvm/lib/Target/ARC/ARCTargetMachine.cpp
View File

@@ -33,11 +33,11 @@ ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T,
"e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
"f32:32:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, getRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenCommonTMImpl(T,
"e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
"f32:32:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, getRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, std::string(CPU), std::string(FS), *this) {
initAsmInfo();

4
llvm/lib/Target/ARC/ARCTargetMachine.h
View File

@@ -14,14 +14,14 @@
#define LLVM_LIB_TARGET_ARC_ARCTARGETMACHINE_H
#include "ARCSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
class TargetPassConfig;
class ARCTargetMachine : public LLVMTargetMachine {
class ARCTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
ARCSubtarget Subtarget;

7
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@@ -220,9 +220,10 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenTargetMachineImpl(T, computeDataLayout(TT, CPU, Options, isLittle),
TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TargetABI(computeTargetABI(TT, CPU, Options)),
TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {

3
llvm/lib/Target/ARM/ARMTargetMachine.h
View File

@@ -17,6 +17,7 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Target/TargetMachine.h"
#include <memory>
@@ -24,7 +25,7 @@
namespace llvm {
class ARMBaseTargetMachine : public LLVMTargetMachine {
class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
public:
enum ARMABI {
ARM_ABI_UNKNOWN,

6
llvm/lib/Target/AVR/AVRTargetMachine.cpp
View File

@@ -49,9 +49,9 @@ AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenTargetMachineImpl(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
SubTarget(TT, std::string(getCPU(CPU)), std::string(FS), *this) {
this->TLOF = std::make_unique<AVRTargetObjectFile>();
initAsmInfo();

4
llvm/lib/Target/AVR/AVRTargetMachine.h
View File

@@ -13,8 +13,8 @@
#ifndef LLVM_AVR_TARGET_MACHINE_H
#define LLVM_AVR_TARGET_MACHINE_H
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
#include "AVRFrameLowering.h"
#include "AVRISelLowering.h"
@@ -27,7 +27,7 @@
namespace llvm {
/// A generic AVR implementation.
class AVRTargetMachine : public LLVMTargetMachine {
class AVRTargetMachine : public CodeGenTargetMachineImpl {
public:
AVRTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,

6
llvm/lib/Target/BPF/BPFTargetMachine.cpp
View File

@@ -69,9 +69,9 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, std::string(CPU), std::string(FS), *this) {
initAsmInfo();

4
llvm/lib/Target/BPF/BPFTargetMachine.h
View File

@@ -14,11 +14,11 @@
#define LLVM_LIB_TARGET_BPF_BPFTARGETMACHINE_H
#include "BPFSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
class BPFTargetMachine : public LLVMTargetMachine {
class BPFTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
BPFSubtarget Subtarget;

6
llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
View File

@@ -54,9 +54,9 @@ CSKYTargetMachine::CSKYTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
RM.value_or(Reloc::Static),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenCommonTMImpl(T, computeDataLayout(TT), TT, CPU, FS, Options,
RM.value_or(Reloc::Static),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<CSKYELFTargetObjectFile>()) {
initAsmInfo();
}

4
llvm/lib/Target/CSKY/CSKYTargetMachine.h
View File

@@ -14,13 +14,13 @@
#define LLVM_LIB_TARGET_CSKY_CSKYTARGETMACHINE_H
#include "CSKYSubtarget.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
#include <optional>
namespace llvm {
class CSKYTargetMachine : public LLVMTargetMachine {
class CSKYTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
mutable StringMap<std::unique_ptr<CSKYSubtarget>> SubtargetMap;

10
llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
View File

@@ -108,11 +108,11 @@ DirectXTargetMachine::DirectXTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T,
"e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-"
"f32:32-f64:64-n8:16:32:64",
TT, CPU, FS, Options, Reloc::Static, CodeModel::Small,
OL),
: CodeGenCommonTMImpl(
T,
"e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-"
"f32:32-f64:64-n8:16:32:64",
TT, CPU, FS, Options, Reloc::Static, CodeModel::Small, OL),
TLOF(std::make_unique<DXILTargetObjectFile>()),
Subtarget(std::make_unique<DirectXSubtarget>(TT, CPU, FS, *this)) {
initAsmInfo();

4
llvm/lib/Target/DirectX/DirectXTargetMachine.h
View File

@@ -12,12 +12,12 @@
#define LLVM_DIRECTX_DIRECTXTARGETMACHINE_H
#include "DirectXSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
class Function;
class DirectXTargetMachine : public LLVMTargetMachine {
class DirectXTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
std::unique_ptr<DirectXSubtarget> Subtarget;

2
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@@ -274,7 +274,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
// Specify the vector alignment explicitly. For v512x1, the calculated
// alignment would be 512*alignment(i1), which is 512 bytes, instead of
// the required minimum of 64 bytes.
: LLVMTargetMachine(
: CodeGenTargetMachineImpl(
T,
"e-m:e-p:32:32:32-a:0-n16:32-"
"i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"

4
llvm/lib/Target/Hexagon/HexagonTargetMachine.h
View File

@@ -16,12 +16,12 @@
#include "HexagonInstrInfo.h"
#include "HexagonSubtarget.h"
#include "HexagonTargetObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
class HexagonTargetMachine : public LLVMTargetMachine {
class HexagonTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
HexagonSubtarget Subtarget;
mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;

8
llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
View File

@@ -60,10 +60,10 @@ LanaiTargetMachine::LanaiTargetMachine(
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CodeModel, CodeGenOptLevel OptLevel,
bool JIT)
: LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CodeModel, CodeModel::Medium),
OptLevel),
: CodeGenTargetMachineImpl(
T, computeDataLayout(), TT, Cpu, FeatureString, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CodeModel, CodeModel::Medium), OptLevel),
Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(),
OptLevel),
TLOF(new LanaiTargetObjectFile()) {

4
llvm/lib/Target/Lanai/LanaiTargetMachine.h
View File

@@ -17,12 +17,12 @@
#include "LanaiInstrInfo.h"
#include "LanaiSelectionDAGInfo.h"
#include "LanaiSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
class LanaiTargetMachine : public LLVMTargetMachine {
class LanaiTargetMachine : public CodeGenTargetMachineImpl {
LanaiSubtarget Subtarget;
std::unique_ptr<TargetLoweringObjectFile> TLOF;

6
llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
View File

@@ -89,9 +89,9 @@ LoongArchTargetMachine::LoongArchTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveLoongArchCodeModel(TT, CM), OL),
: CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveLoongArchCodeModel(TT, CM), OL),
TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
initAsmInfo();
}

4
llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
View File

@@ -14,12 +14,12 @@
#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHTARGETMACHINE_H
#include "LoongArchSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
class LoongArchTargetMachine : public LLVMTargetMachine {
class LoongArchTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
mutable StringMap<std::unique_ptr<LoongArchSubtarget>> SubtargetMap;

6
llvm/lib/Target/M68k/M68kTargetMachine.cpp
View File

@@ -100,9 +100,9 @@ M68kTargetMachine::M68kTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,
Options, getEffectiveRelocModel(TT, RM),
::getEffectiveCodeModel(CM, JIT), OL),
: CodeGenCommonTMImpl(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,
Options, getEffectiveRelocModel(TT, RM),
::getEffectiveCodeModel(CM, JIT), OL),
TLOF(std::make_unique<M68kELFTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();

4
llvm/lib/Target/M68k/M68kTargetMachine.h
View File

@@ -17,10 +17,10 @@
#include "M68kSubtarget.h"
#include "MCTargetDesc/M68kMCTargetDesc.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include <optional>
@@ -28,7 +28,7 @@ namespace llvm {
class formatted_raw_ostream;
class M68kRegisterInfo;
class M68kTargetMachine : public LLVMTargetMachine {
class M68kTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
M68kSubtarget Subtarget;

6
llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@@ -44,9 +44,9 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,
Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenTargetMachineImpl(T, computeDataLayout(TT, CPU, Options), TT, CPU,
FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, std::string(CPU), std::string(FS), *this) {
initAsmInfo();

4
llvm/lib/Target/MSP430/MSP430TargetMachine.h
View File

@@ -15,7 +15,7 @@
#define LLVM_LIB_TARGET_MSP430_MSP430TARGETMACHINE_H
#include "MSP430Subtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
@@ -23,7 +23,7 @@ class StringRef;
/// MSP430TargetMachine
///
class MSP430TargetMachine : public LLVMTargetMachine {
class MSP430TargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
MSP430Subtarget Subtarget;

4
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
View File

@@ -805,8 +805,8 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
ELFObjectWriter &W = getStreamer().getWriter();
// It's possible that MCObjectFileInfo isn't fully initialized at this point
// due to an initialization order problem where LLVMTargetMachine creates the
// target streamer before TargetLoweringObjectFile calls
// due to an initialization order problem where CodeGenCommonTMImpl creates
// the target streamer before TargetLoweringObjectFile calls
// InitializeMCObjectFileInfo. There doesn't seem to be a single place that
// covers all cases so this statement covers most cases and direct object
// emission must call setPic() once MCObjectFileInfo has been initialized. The

7
llvm/lib/Target/Mips/MipsTargetMachine.cpp
View File

@@ -129,9 +129,10 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT,
bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenTargetMachineImpl(T, computeDataLayout(TT, CPU, Options, isLittle),
TT, CPU, FS, Options,
getEffectiveRelocModel(JIT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
isLittle(isLittle), TLOF(createTLOF(getTargetTriple())),
ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
Subtarget(nullptr),

4
llvm/lib/Target/Mips/MipsTargetMachine.h
View File

@@ -17,14 +17,14 @@
#include "MipsSubtarget.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Target/TargetMachine.h"
#include <memory>
#include <optional>
namespace llvm {
class MipsTargetMachine : public LLVMTargetMachine {
class MipsTargetMachine : public CodeGenTargetMachineImpl {
bool isLittle;
std::unique_ptr<TargetLoweringObjectFile> TLOF;
// Selected ABI

4
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
View File

@@ -209,8 +209,8 @@ bool NVPTXAsmPrinter::lowerImageHandleOperand(const MachineInstr *MI,
void NVPTXAsmPrinter::lowerImageHandleSymbol(unsigned Index, MCOperand &MCOp) {
// Ewwww
LLVMTargetMachine &TM = const_cast<LLVMTargetMachine&>(MF->getTarget());
NVPTXTargetMachine &nvTM = static_cast<NVPTXTargetMachine&>(TM);
TargetMachine &TM = const_cast<TargetMachine &>(MF->getTarget());
NVPTXTargetMachine &nvTM = static_cast<NVPTXTargetMachine &>(TM);
const NVPTXMachineFunctionInfo *MFI = MF->getInfo<NVPTXMachineFunctionInfo>();
const char *Sym = MFI->getImageHandleSymbol(Index);
StringRef SymName = nvTM.getStrPool().save(Sym);

7
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@@ -153,9 +153,10 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
CodeGenOptLevel OL, bool is64bit)
// The pic relocation model is used regardless of what the client has
// specified, as it is the only relocation model currently supported.
: LLVMTargetMachine(T, computeDataLayout(is64bit, UseShortPointersOpt), TT,
CPU, FS, Options, Reloc::PIC_,
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenTargetMachineImpl(T,
computeDataLayout(is64bit, UseShortPointersOpt),
TT, CPU, FS, Options, Reloc::PIC_,
getEffectiveCodeModel(CM, CodeModel::Small), OL),
is64bit(is64bit), TLOF(std::make_unique<NVPTXTargetObjectFile>()),
Subtarget(TT, std::string(CPU), std::string(FS), *this),
StrPool(StrAlloc) {

4
llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
View File

@@ -14,7 +14,7 @@
#define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H
#include "NVPTXSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
#include <utility>
@@ -22,7 +22,7 @@ namespace llvm {
/// NVPTXTargetMachine
///
class NVPTXTargetMachine : public LLVMTargetMachine {
class NVPTXTargetMachine : public CodeGenTargetMachineImpl {
bool is64bit;
std::unique_ptr<TargetLoweringObjectFile> TLOF;
NVPTX::DrvInterface drvInterface;

12
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@@ -345,18 +345,18 @@ static ScheduleDAGInstrs *createPPCPostMachineScheduler(
// The FeatureString here is a little subtle. We are modifying the feature
// string with what are (currently) non-function specific overrides as it goes
// into the LLVMTargetMachine constructor and then using the stored value in the
// Subtarget constructor below it.
// into the CodeGenCommonTMImpl constructor and then using the stored value in
// the Subtarget constructor below it.
PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
computeFSAdditions(FS, OL, TT), Options,
getEffectiveRelocModel(TT, RM),
getEffectivePPCCodeModel(TT, CM, JIT), OL),
: CodeGenTargetMachineImpl(T, getDataLayoutString(TT), TT, CPU,
computeFSAdditions(FS, OL, TT), Options,
getEffectiveRelocModel(TT, RM),
getEffectivePPCCodeModel(TT, CM, JIT), OL),
TLOF(createTLOF(getTargetTriple())),
TargetABI(computeTargetABI(TT, Options)),
Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {

4
llvm/lib/Target/PowerPC/PPCTargetMachine.h
View File

@@ -15,15 +15,15 @@
#include "PPCInstrInfo.h"
#include "PPCSubtarget.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
#include <optional>
namespace llvm {
/// Common code between 32-bit and 64-bit PowerPC targets.
///
class PPCTargetMachine final : public LLVMTargetMachine {
class PPCTargetMachine final : public CodeGenTargetMachineImpl {
public:
enum PPCABI { PPC_ABI_UNKNOWN, PPC_ABI_ELFv1, PPC_ABI_ELFv2 };
enum Endian { NOT_DETECTED, LITTLE, BIG };

6
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
View File

@@ -170,9 +170,9 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT, Options), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenTargetMachineImpl(T, computeDataLayout(TT, Options), TT, CPU, FS,
Options, getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
initAsmInfo();

4
llvm/lib/Target/RISCV/RISCVTargetMachine.h
View File

@@ -15,13 +15,13 @@
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
#include <optional>
namespace llvm {
class RISCVTargetMachine : public LLVMTargetMachine {
class RISCVTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;

5
llvm/lib/Target/SPIRV/SPIRVAPI.cpp
View File

@@ -158,10 +158,9 @@ SPIRVTranslateModule(Module *M, std::string &SpirvObj, std::string &ErrMsg,
TargetLibraryInfoImpl TLII(Triple(M->getTargetTriple()));
legacy::PassManager PM;
PM.add(new TargetLibraryInfoWrapperPass(TLII));
LLVMTargetMachine &LLVMTM = static_cast<LLVMTargetMachine &>(*Target);
MachineModuleInfoWrapperPass *MMIWP =
new MachineModuleInfoWrapperPass(&LLVMTM);
const_cast<TargetLoweringObjectFile *>(LLVMTM.getObjFileLowering())
new MachineModuleInfoWrapperPass(Target.get());
const_cast<TargetLoweringObjectFile *>(Target->getObjFileLowering())
->Initialize(MMIWP->getMMI().getContext(), *Target);
SmallString<4096> OutBuffer;

6
llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
View File

@@ -80,9 +80,9 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<SPIRVTargetObjectFile>()),
Subtarget(TT, CPU.str(), FS.str(), *this) {
initAsmInfo();

4
llvm/lib/Target/SPIRV/SPIRVTargetMachine.h
View File

@@ -14,11 +14,11 @@
#define LLVM_LIB_TARGET_SPIRV_SPIRVTARGETMACHINE_H
#include "SPIRVSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
class SPIRVTargetMachine : public LLVMTargetMachine {
class SPIRVTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
SPIRVSubtarget Subtarget;

11
llvm/lib/Target/Sparc/SparcTargetMachine.cpp
View File

@@ -107,11 +107,12 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT,
bool is64bit)
: LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveSparcCodeModel(
CM, getEffectiveRelocModel(RM), is64bit, JIT),
OL),
: CodeGenTargetMachineImpl(
T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveSparcCodeModel(CM, getEffectiveRelocModel(RM), is64bit,
JIT),
OL),
TLOF(std::make_unique<SparcELFTargetObjectFile>()), is64Bit(is64bit) {
initAsmInfo();
}

3
llvm/lib/Target/Sparc/SparcTargetMachine.h
View File

@@ -15,12 +15,13 @@
#include "SparcInstrInfo.h"
#include "SparcSubtarget.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/Target/TargetMachine.h"
#include <optional>
namespace llvm {
class SparcTargetMachine : public LLVMTargetMachine {
class SparcTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
bool is64Bit;
mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;

2
llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@@ -158,7 +158,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(
: CodeGenTargetMachineImpl(
T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT),

3
llvm/lib/Target/SystemZ/SystemZTargetMachine.h
View File

@@ -17,6 +17,7 @@
#include "SystemZSubtarget.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Target/TargetMachine.h"
#include <memory>
@@ -24,7 +25,7 @@
namespace llvm {
class SystemZTargetMachine : public LLVMTargetMachine {
class SystemZTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
mutable StringMap<std::unique_ptr<SystemZSubtarget>> SubtargetMap;

6
llvm/lib/Target/VE/VETargetMachine.cpp
View File

@@ -89,9 +89,9 @@ VETargetMachine::VETargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(createTLOF()),
Subtarget(TT, std::string(CPU), std::string(FS), *this) {
initAsmInfo();

4
llvm/lib/Target/VE/VETargetMachine.h
View File

@@ -15,12 +15,12 @@
#include "VEInstrInfo.h"
#include "VESubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
class VETargetMachine : public LLVMTargetMachine {
class VETargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
VESubtarget Subtarget;
// Hold Strings that can be free'd all together with VETargetMachine

6
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp
View File

@@ -47,9 +47,9 @@ WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo(const Triple &T,
// When compilation is done on a cpp file by clang, the exception model info
// is stored in LangOptions, which is later used to set the info in
// TargetOptions and then MCAsmInfo in LLVMTargetMachine::initAsmInfo(). But
// this process does not happen when compiling bitcode directly with clang, so
// we make sure this info is set correctly.
// TargetOptions and then MCAsmInfo in CodeGenTargetMachine::initAsmInfo().
// But this process does not happen when compiling bitcode directly with
// clang, so we make sure this info is set correctly.
if (WebAssembly::WasmEnableEH || WebAssembly::WasmEnableSjLj)
ExceptionsType = ExceptionHandling::Wasm;
}

2
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
View File

@@ -115,7 +115,7 @@ WebAssemblyTargetMachine::WebAssemblyTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(
: CodeGenTargetMachineImpl(
T,
TT.isArch64Bit()
? (TT.isOSEmscripten() ? "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"

4
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
View File

@@ -16,12 +16,12 @@
#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYTARGETMACHINE_H
#include "WebAssemblySubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
class WebAssemblyTargetMachine final : public LLVMTargetMachine {
class WebAssemblyTargetMachine final : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
mutable StringMap<std::unique_ptr<WebAssemblySubtarget>> SubtargetMap;
bool UsesMultivalueABI = false;

8
llvm/lib/Target/X86/X86TargetMachine.cpp
View File

@@ -233,11 +233,9 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(
T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, JIT, RM),
getEffectiveX86CodeModel(TT, CM, JIT),
OL),
: CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, JIT, RM),
getEffectiveX86CodeModel(TT, CM, JIT), OL),
TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
// On PS4/PS5, the "return address" of a 'noreturn' call must still be within
// the calling function. Note that this also includes __stack_chk_fail,

4
llvm/lib/Target/X86/X86TargetMachine.h
View File

@@ -15,8 +15,8 @@
#include "X86Subtarget.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Target/TargetMachine.h"
#include <memory>
#include <optional>
@@ -25,7 +25,7 @@ namespace llvm {
class StringRef;
class TargetTransformInfo;
class X86TargetMachine final : public LLVMTargetMachine {
class X86TargetMachine final : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
mutable StringMap<std::unique_ptr<X86Subtarget>> SubtargetMap;
// True if this is used in JIT.

2
llvm/lib/Target/XCore/XCoreTargetMachine.cpp
View File

@@ -48,7 +48,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(
: CodeGenTargetMachineImpl(
T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, getEffectiveRelocModel(RM),
getEffectiveXCoreCodeModel(CM), OL),

4
llvm/lib/Target/XCore/XCoreTargetMachine.h
View File

@@ -15,15 +15,15 @@
#include "XCoreSubtarget.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Target/TargetMachine.h"
#include <memory>
#include <optional>
namespace llvm {
class StringRef;
class XCoreTargetMachine : public LLVMTargetMachine {
class XCoreTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
XCoreSubtarget Subtarget;

6
llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
View File

@@ -50,9 +50,9 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT,
bool IsLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
: CodeGenCommonTMImpl(T, computeDataLayout(TT, CPU, Options, IsLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
initAsmInfo();
}

4
llvm/lib/Target/Xtensa/XtensaTargetMachine.h
View File

@@ -16,13 +16,13 @@
#define LLVM_LIB_TARGET_XTENSA_XTENSATARGETMACHINE_H
#include "XtensaSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include <optional>
namespace llvm {
extern Target TheXtensaTarget;
class XtensaTargetMachine : public LLVMTargetMachine {
class XtensaTargetMachine : public CodeGenTargetMachineImpl {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
public:
XtensaTargetMachine(const Target &T, const Triple &TT, StringRef CPU,

8
llvm/tools/llc/NewPMDriver.cpp
View File

@@ -99,8 +99,6 @@ int llvm::compileModuleWithNewPM(
return 1;
}
LLVMTargetMachine &LLVMTM = static_cast<LLVMTargetMachine &>(*Target);
raw_pwrite_stream *OS = &Out->os();
// Fetch options from TargetPassConfig
@@ -109,12 +107,12 @@ int llvm::compileModuleWithNewPM(
Opt.DebugPM = DebugPM;
Opt.RegAlloc = RegAlloc;
MachineModuleInfo MMI(&LLVMTM);
MachineModuleInfo MMI(Target.get());
PassInstrumentationCallbacks PIC;
StandardInstrumentations SI(Context, Opt.DebugPM,
VK == VerifierKind::EachPass);
registerCodeGenCallback(PIC, LLVMTM);
registerCodeGenCallback(PIC, *Target);
MachineFunctionAnalysisManager MFAM;
LoopAnalysisManager LAM;
@@ -158,7 +156,7 @@ int llvm::compileModuleWithNewPM(
if (MIR->parseMachineFunctions(*M, MAM))
return 1;
} else {
ExitOnErr(LLVMTM.buildCodeGenPipeline(
ExitOnErr(Target->buildCodeGenPipeline(
MPM, *OS, DwoOut ? &DwoOut->os() : nullptr, FileType, Opt, &PIC));
}

7
llvm/tools/llc/llc.cpp
View File

@@ -685,9 +685,8 @@ static int compileModule(char **argv, LLVMContext &Context) {
}
const char *argv0 = argv[0];
LLVMTargetMachine &LLVMTM = static_cast<LLVMTargetMachine &>(*Target);
MachineModuleInfoWrapperPass *MMIWP =
new MachineModuleInfoWrapperPass(&LLVMTM);
new MachineModuleInfoWrapperPass(Target.get());
// Construct a custom pass pipeline that starts after instruction
// selection.
@@ -698,7 +697,7 @@ static int compileModule(char **argv, LLVMContext &Context) {
delete MMIWP;
return 1;
}
TargetPassConfig *PTPC = LLVMTM.createPassConfig(PM);
TargetPassConfig *PTPC = Target->createPassConfig(PM);
TargetPassConfig &TPC = *PTPC;
if (TPC.hasLimitedCodeGenPipeline()) {
WithColor::warning(errs(), argv[0])
@@ -726,7 +725,7 @@ static int compileModule(char **argv, LLVMContext &Context) {
reportError("target does not support generation of this file type");
}
const_cast<TargetLoweringObjectFile *>(LLVMTM.getObjFileLowering())
const_cast<TargetLoweringObjectFile *>(Target->getObjFileLowering())
->Initialize(MMIWP->getMMI().getContext(), *Target);
if (MIR) {
assert(MMIWP && "Forgot to create MMIWP?");

8
llvm/tools/llvm-exegesis/lib/Assembler.cpp
View File

@@ -232,9 +232,7 @@ createModule(const std::unique_ptr<LLVMContext> &Context, const DataLayout &DL)
BitVector getFunctionReservedRegs(const TargetMachine &TM) {
std::unique_ptr<LLVMContext> Context = std::make_unique<LLVMContext>();
std::unique_ptr<Module> Module = createModule(Context, TM.createDataLayout());
// TODO: This only works for targets implementing LLVMTargetMachine.
const LLVMTargetMachine &LLVMTM = static_cast<const LLVMTargetMachine &>(TM);
auto MMIWP = std::make_unique<MachineModuleInfoWrapperPass>(&LLVMTM);
auto MMIWP = std::make_unique<MachineModuleInfoWrapperPass>(&TM);
MachineFunction &MF = createVoidVoidPtrMachineFunction(
FunctionID, Module.get(), &MMIWP->getMMI());
// Saving reserved registers for client.
@@ -242,7 +240,7 @@ BitVector getFunctionReservedRegs(const TargetMachine &TM) {
}
Error assembleToStream(const ExegesisTarget &ET,
std::unique_ptr<LLVMTargetMachine> TM,
std::unique_ptr<TargetMachine> TM,
ArrayRef<unsigned> LiveIns, const FillFunction &Fill,
raw_pwrite_stream &AsmStream, const BenchmarkKey &Key,
bool GenerateMemoryInstructions) {
@@ -358,7 +356,7 @@ object::OwningBinary<object::ObjectFile> getObjectFromFile(StringRef Filename) {
}
Expected<ExecutableFunction> ExecutableFunction::create(
std::unique_ptr<LLVMTargetMachine> TM,
std::unique_ptr<TargetMachine> TM,
object::OwningBinary<object::ObjectFile> &&ObjectFileHolder) {
assert(ObjectFileHolder.getBinary() && "cannot create object file");
std::unique_ptr<LLVMContext> Ctx = std::make_unique<LLVMContext>();

4
llvm/tools/llvm-exegesis/lib/Assembler.h
View File

@@ -89,7 +89,7 @@ using FillFunction = std::function<void(FunctionFiller &)>;
// epilogue. Once the MachineFunction is ready, it is assembled for TM to
// AsmStream, the temporary function is eventually discarded.
Error assembleToStream(const ExegesisTarget &ET,
std::unique_ptr<LLVMTargetMachine> TM,
std::unique_ptr<TargetMachine> TM,
ArrayRef<unsigned> LiveIns, const FillFunction &Fill,
raw_pwrite_stream &AsmStreamm, const BenchmarkKey &Key,
bool GenerateMemoryInstructions);
@@ -107,7 +107,7 @@ object::OwningBinary<object::ObjectFile> getObjectFromFile(StringRef Filename);
class ExecutableFunction {
public:
static Expected<ExecutableFunction>
create(std::unique_ptr<LLVMTargetMachine> TM,
create(std::unique_ptr<TargetMachine> TM,
object::OwningBinary<object::ObjectFile> &&ObjectFileHolder);
// Retrieves the function as an array of bytes.

11
llvm/tools/llvm-exegesis/lib/LlvmState.cpp
View File

@@ -56,9 +56,8 @@ Expected<LLVMState> LLVMState::Create(std::string TripleName,
inconvertibleErrorCode());
}
const TargetOptions Options;
std::unique_ptr<const TargetMachine> TM(
static_cast<LLVMTargetMachine *>(TheTarget->createTargetMachine(
TripleName, CpuName, Features, Options, Reloc::Model::Static)));
std::unique_ptr<const TargetMachine> TM(TheTarget->createTargetMachine(
TripleName, CpuName, Features, Options, Reloc::Model::Static));
if (!TM) {
return make_error<StringError>("unable to create target machine",
inconvertibleErrorCode());
@@ -91,13 +90,13 @@ LLVMState::LLVMState(std::unique_ptr<const TargetMachine> TM,
IC.reset(new InstructionsCache(getInstrInfo(), getRATC()));
}
std::unique_ptr<LLVMTargetMachine> LLVMState::createTargetMachine() const {
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
std::unique_ptr<TargetMachine> LLVMState::createTargetMachine() const {
return std::unique_ptr<TargetMachine>(
TheTargetMachine->getTarget().createTargetMachine(
TheTargetMachine->getTargetTriple().normalize(),
TheTargetMachine->getTargetCPU(),
TheTargetMachine->getTargetFeatureString(), TheTargetMachine->Options,
Reloc::Model::Static)));
Reloc::Model::Static));
}
std::optional<MCRegister>

2
llvm/tools/llvm-exegesis/lib/LlvmState.h
View File

@@ -49,7 +49,7 @@ public:
bool UseDummyPerfCounters = false);
const TargetMachine &getTargetMachine() const { return *TheTargetMachine; }
std::unique_ptr<LLVMTargetMachine> createTargetMachine() const;
std::unique_ptr<TargetMachine> createTargetMachine() const;
const ExegesisTarget &getExegesisTarget() const { return *TheExegesisTarget; }

7
llvm/tools/llvm-reduce/ReducerWorkItem.cpp
View File

@@ -521,9 +521,7 @@ ReducerWorkItem::clone(const TargetMachine *TM) const {
// MachineModuleInfo contains a lot of other state used during codegen which
// we won't be using here, but we should be able to ignore it (although this
// is pretty ugly).
const LLVMTargetMachine *LLVMTM =
static_cast<const LLVMTargetMachine *>(TM);
CloneMMM->MMI = std::make_unique<MachineModuleInfo>(LLVMTM);
CloneMMM->MMI = std::make_unique<MachineModuleInfo>(TM);
for (const Function &F : getModule()) {
if (auto *MF = MMI->getMachineFunction(F))
@@ -839,9 +837,8 @@ llvm::parseReducerWorkItem(StringRef ToolName, StringRef Filename,
};
std::unique_ptr<Module> M = MParser->parseIRModule(SetDataLayout);
LLVMTargetMachine *LLVMTM = static_cast<LLVMTargetMachine *>(TM.get());
MMM->MMI = std::make_unique<MachineModuleInfo>(LLVMTM);
MMM->MMI = std::make_unique<MachineModuleInfo>(TM.get());
MParser->parseMachineFunctions(*M, *MMM->MMI);
MMM->M = std::move(M);
} else {

8
llvm/tools/opt/optdriver.cpp
View File

@@ -801,9 +801,11 @@ extern "C" int optMain(
}
if (TM) {
// FIXME: We should dyn_cast this when supported.
auto &LTM = static_cast<LLVMTargetMachine &>(*TM);
Pass *TPC = LTM.createPassConfig(Passes);
Pass *TPC = TM->createPassConfig(Passes);
if (!TPC) {
errs() << "Target Machine pass config creation failed.\n";
return 1;
}
Passes.add(TPC);
}

6
llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
View File

@@ -44,9 +44,9 @@ protected:
GTEST_SKIP();
TargetOptions Options;
TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
TM = std::unique_ptr<TargetMachine>(
T->createTargetMachine("AArch64", "", "+sve", Options, std::nullopt,
std::nullopt, CodeGenOptLevel::Aggressive)));
std::nullopt, CodeGenOptLevel::Aggressive));
if (!TM)
GTEST_SKIP();
@@ -82,7 +82,7 @@ protected:
}
LLVMContext Context;
std::unique_ptr<LLVMTargetMachine> TM;
std::unique_ptr<TargetMachine> TM;
std::unique_ptr<Module> M;
Function *F;
std::unique_ptr<MachineFunction> MF;

7
llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp
View File

@@ -57,9 +57,8 @@ protected:
GTEST_SKIP();
TargetOptions Options;
TM = std::unique_ptr<LLVMTargetMachine>(
static_cast<LLVMTargetMachine *>(T->createTargetMachine(
"amdgcn--amdpal", "gfx1010", "", Options, std::nullopt)));
TM = std::unique_ptr<TargetMachine>(T->createTargetMachine(
"amdgcn--amdpal", "gfx1010", "", Options, std::nullopt));
if (!TM)
GTEST_SKIP();
@@ -80,7 +79,7 @@ protected:
static std::string PalMDString;
LLVMContext Context;
std::unique_ptr<LLVMTargetMachine> TM;
std::unique_ptr<TargetMachine> TM;
std::unique_ptr<Module> M;
SmallString<1024> Elf;
};

12
llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp
View File

@@ -398,13 +398,13 @@ protected:
auto *AP = TestPrinter->getAP();
AP->addAsmPrinterHandler(std::make_unique<TestHandler>(*this));
LLVMTargetMachine *LLVMTM = static_cast<LLVMTargetMachine *>(&AP->TM);
TargetMachine *TM = &AP->TM;
legacy::PassManager PM;
PM.add(new MachineModuleInfoWrapperPass(LLVMTM));
PM.add(new MachineModuleInfoWrapperPass(TM));
PM.add(TestPrinter->releaseAP()); // Takes ownership of destroying AP
LLVMContext Context;
std::unique_ptr<Module> M(new Module("TestModule", Context));
M->setDataLayout(LLVMTM->createDataLayout());
M->setDataLayout(TM->createDataLayout());
PM.run(*M);
// Now check that we can run it twice.
AP->addAsmPrinterHandler(std::make_unique<TestHandler>(*this));
@@ -448,13 +448,13 @@ protected:
auto *AP = TestPrinter->getAP();
AP->addDebugHandler(std::make_unique<TestDebugHandler>(*this, AP));
LLVMTargetMachine *LLVMTM = static_cast<LLVMTargetMachine *>(&AP->TM);
TargetMachine *TM = &AP->TM;
legacy::PassManager PM;
PM.add(new MachineModuleInfoWrapperPass(LLVMTM));
PM.add(new MachineModuleInfoWrapperPass(TM));
PM.add(TestPrinter->releaseAP()); // Takes ownership of destroying AP
LLVMContext Context;
std::unique_ptr<Module> M(new Module("TestModule", Context));
M->setDataLayout(LLVMTM->createDataLayout());
M->setDataLayout(TM->createDataLayout());
PM.run(*M);
// Now check that we can run it twice.
AP->addDebugHandler(std::make_unique<TestDebugHandler>(*this, AP));

2
llvm/unittests/CodeGen/CCStateTest.cpp
View File

@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
@@ -16,7 +17,6 @@
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Target/TargetMachine.h"
#include "gtest/gtest.h"
using namespace llvm;

17
llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp
View File

@@ -29,8 +29,7 @@ operator<<(std::ostream &OS, const MachineFunction &MF) {
}
std::unique_ptr<LLVMTargetMachine>
AArch64GISelMITest::createTargetMachine() const {
std::unique_ptr<TargetMachine> AArch64GISelMITest::createTargetMachine() const {
Triple TargetTriple("aarch64--");
std::string Error;
const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
@@ -38,9 +37,9 @@ AArch64GISelMITest::createTargetMachine() const {
return nullptr;
TargetOptions Options;
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
return std::unique_ptr<TargetMachine>(
T->createTargetMachine("AArch64", "", "", Options, std::nullopt,
std::nullopt, CodeGenOptLevel::Aggressive)));
std::nullopt, CodeGenOptLevel::Aggressive));
}
void AArch64GISelMITest::getTargetTestModuleString(SmallString<512> &S,
@@ -67,8 +66,7 @@ body: |
.toNullTerminatedStringRef(S);
}
std::unique_ptr<LLVMTargetMachine>
AMDGPUGISelMITest::createTargetMachine() const {
std::unique_ptr<TargetMachine> AMDGPUGISelMITest::createTargetMachine() const {
Triple TargetTriple("amdgcn-amd-amdhsa");
std::string Error;
const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
@@ -76,10 +74,9 @@ AMDGPUGISelMITest::createTargetMachine() const {
return nullptr;
TargetOptions Options;
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine("amdgcn-amd-amdhsa", "gfx900", "", Options,
std::nullopt, std::nullopt,
CodeGenOptLevel::Aggressive)));
return std::unique_ptr<TargetMachine>(T->createTargetMachine(
"amdgcn-amd-amdhsa", "gfx900", "", Options, std::nullopt, std::nullopt,
CodeGenOptLevel::Aggressive));
}
void AMDGPUGISelMITest::getTargetTestModuleString(

12
llvm/unittests/CodeGen/GlobalISel/GISelMITest.h
View File

@@ -74,7 +74,7 @@ parseMIR(LLVMContext &Context, std::unique_ptr<MIRParser> &MIR,
return M;
}
static std::pair<std::unique_ptr<Module>, std::unique_ptr<MachineModuleInfo>>
createDummyModule(LLVMContext &Context, const LLVMTargetMachine &TM,
createDummyModule(LLVMContext &Context, const TargetMachine &TM,
StringRef MIRString, const char *FuncName) {
std::unique_ptr<MIRParser> MIR;
auto MMI = std::make_unique<MachineModuleInfo>(&TM);
@@ -102,8 +102,8 @@ class GISelMITest : public ::testing::Test {
protected:
GISelMITest() : ::testing::Test() {}
/// Prepare a target specific LLVMTargetMachine.
virtual std::unique_ptr<LLVMTargetMachine> createTargetMachine() const = 0;
/// Prepare a target specific TargetMachine.
virtual std::unique_ptr<TargetMachine> createTargetMachine() const = 0;
/// Get the stub sample MIR test function.
virtual void getTargetTestModuleString(SmallString<512> &S,
@@ -127,7 +127,7 @@ protected:
}
LLVMContext Context;
std::unique_ptr<LLVMTargetMachine> TM;
std::unique_ptr<TargetMachine> TM;
MachineFunction *MF;
std::pair<std::unique_ptr<Module>, std::unique_ptr<MachineModuleInfo>>
ModuleMMIPair;
@@ -138,13 +138,13 @@ protected:
};
class AArch64GISelMITest : public GISelMITest {
std::unique_ptr<LLVMTargetMachine> createTargetMachine() const override;
std::unique_ptr<TargetMachine> createTargetMachine() const override;
void getTargetTestModuleString(SmallString<512> &S,
StringRef MIRFunc) const override;
};
class AMDGPUGISelMITest : public GISelMITest {
std::unique_ptr<LLVMTargetMachine> createTargetMachine() const override;
std::unique_ptr<TargetMachine> createTargetMachine() const override;
void getTargetTestModuleString(SmallString<512> &S,
StringRef MIRFunc) const override;
};

8
llvm/unittests/CodeGen/InstrRefLDVTest.cpp
View File

@@ -6,6 +6,7 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/MIRParser/MIRParser.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
@@ -21,7 +22,6 @@
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "../lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h"
@@ -90,11 +90,11 @@ public:
Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &*Mod);
unsigned FunctionNum = 42;
MMI = std::make_unique<MachineModuleInfo>((LLVMTargetMachine *)&*Machine);
MMI = std::make_unique<MachineModuleInfo>(Machine.get());
const TargetSubtargetInfo &STI = *Machine->getSubtargetImpl(*F);
MF = std::make_unique<MachineFunction>(*F, (LLVMTargetMachine &)*Machine,
STI, MMI->getContext(), FunctionNum);
MF = std::make_unique<MachineFunction>(*F, *Machine, STI, MMI->getContext(),
FunctionNum);
// Create metadata: CU, subprogram, some blocks and an inline function
// scope.

2
llvm/unittests/CodeGen/LexicalScopesTest.cpp
View File

@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/LexicalScopes.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
@@ -25,7 +26,6 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "gtest/gtest.h"

8
llvm/unittests/CodeGen/MFCommon.inc
View File

@@ -104,12 +104,12 @@ static TargetOptions getTargetOptionsForBogusMachine() {
return Opts;
}
class BogusTargetMachine : public LLVMTargetMachine {
class BogusTargetMachine : public CodeGenTargetMachineImpl {
public:
BogusTargetMachine()
: LLVMTargetMachine(Target(), "", Triple(""), "", "",
getTargetOptionsForBogusMachine(), Reloc::Static,
CodeModel::Small, CodeGenOptLevel::Default),
: CodeGenTargetMachineImpl(
Target(), "", Triple(""), "", "", getTargetOptionsForBogusMachine(),
Reloc::Static, CodeModel::Small, CodeGenOptLevel::Default),
ST(*this) {}
~BogusTargetMachine() override {}

2
llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp
View File

@@ -8,6 +8,7 @@
#include "../../lib/CodeGen/MLRegAllocEvictAdvisor.h"
#include "llvm/Analysis/NoInferenceModelRunner.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
@@ -21,7 +22,6 @@
#include "llvm/Support/Allocator.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/Triple.h"
#include "gmock/gmock.h"

2
llvm/unittests/CodeGen/MachineBasicBlockTest.cpp
View File

@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -20,7 +21,6 @@
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Target/TargetMachine.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"

3
llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp
View File

@@ -60,8 +60,7 @@ public:
T->createTargetMachine("X86", "", "", Options, std::nullopt));
if (!TM)
GTEST_SKIP();
MMI = std::make_unique<MachineModuleInfo>(
static_cast<LLVMTargetMachine *>(TM.get()));
MMI = std::make_unique<MachineModuleInfo>(TM.get());
PassBuilder PB(TM.get());
PB.registerModuleAnalyses(MAM);

2
llvm/unittests/CodeGen/MachineInstrTest.cpp
View File

@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -25,7 +26,6 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/Triple.h"
#include "gmock/gmock.h"

2
llvm/unittests/CodeGen/MachineOperandTest.cpp
View File

@@ -8,6 +8,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/ADT/ilist_node.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
@@ -23,7 +24,6 @@
#include "llvm/MC/MCContext.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "gtest/gtest.h"
using namespace llvm;

6
llvm/unittests/CodeGen/PassManagerTest.cpp
View File

@@ -179,10 +179,9 @@ TEST_F(PassManagerTest, Basic) {
if (!TM)
GTEST_SKIP();
LLVMTargetMachine *LLVMTM = static_cast<LLVMTargetMachine *>(TM.get());
M->setDataLayout(TM->createDataLayout());
MachineModuleInfo MMI(LLVMTM);
MachineModuleInfo MMI(TM.get());
MachineFunctionAnalysisManager MFAM;
LoopAnalysisManager LAM;
@@ -229,10 +228,9 @@ TEST_F(PassManagerTest, DiagnosticHandler) {
if (!TM)
GTEST_SKIP();
LLVMTargetMachine *LLVMTM = static_cast<LLVMTargetMachine *>(TM.get());
M->setDataLayout(TM->createDataLayout());
MachineModuleInfo MMI(LLVMTM);
MachineModuleInfo MMI(TM.get());
LoopAnalysisManager LAM;
MachineFunctionAnalysisManager MFAM;

2
llvm/unittests/CodeGen/RegAllocScoreTest.cpp
View File

@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//
#include "../lib/CodeGen/RegAllocScore.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
@@ -24,7 +25,6 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/Triple.h"
#include "gtest/gtest.h"

Some files were not shown because too many files have changed in this diff Show More