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[AArch64] Add FEAT_FPAC to Neoverse V2 (#133054)

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This feature is implemented in the Neoverse V2 core, but wasn't specified
in the CPU definition.
This commit is contained in:
Sjoerd Meijer
2025-03-26 15:21:21 +00:00
committed by GitHub
parent af663155e6
commit c0cce43739
4 changed files with 5 additions and 2 deletions
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1
clang/test/Driver/aarch64-mcpu-native.c
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@@ -22,6 +22,7 @@
// CHECK-FEAT-NV2: FEAT_FHM Enable FP16 FML instructions
// CHECK-FEAT-NV2: FEAT_FP Enable Armv8.0-A Floating Point Extensions
// CHECK-FEAT-NV2: FEAT_FP16 Enable half-precision floating-point data processing
// CHECK-FEAT-NV2: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-FEAT-NV2: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-FEAT-NV2: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
// CHECK-FEAT-NV2: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons

3
clang/test/Driver/print-enabled-extensions/aarch64-grace.c
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@@ -21,6 +21,7 @@
// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
@@ -59,4 +60,4 @@
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension

1
clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v2.c
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@@ -20,6 +20,7 @@
// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons

2
llvm/lib/Target/AArch64/AArch64Processors.td
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@@ -1015,7 +1015,7 @@ def ProcessorFeatures {
FeatureCCIDX,
FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureDotProd,
FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE,
FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureFPAC];
list<SubtargetFeature> NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
FeatureFullFP16, FeatureLS64, FeatureMTE,
FeaturePerfMon, FeatureRandGen, FeatureSPE,