[LV] Strip unmaintainable MinBWs assert (#136858)
tryToWiden attempts to replace an Instruction with a Constant from SCEV, but forgets to erase the Instruction from the MinBWs map, leading to an assert in VPlanTransforms::truncateToMinimalBitwidths. Going forward, the assertion in truncateToMinimalBitwidths is unmaintainable, as LV could simplify the expression at any point: fix the bug by stripping the unmaintable assertion. Fixes #125278.
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Ramkumar Ramachandra
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@@ -1632,11 +1632,6 @@ static void licm(VPlan &Plan) {
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void VPlanTransforms::truncateToMinimalBitwidths(
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VPlan &Plan, const MapVector<Instruction *, uint64_t> &MinBWs) {
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#ifndef NDEBUG
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// Count the processed recipes and cross check the count later with MinBWs
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// size, to make sure all entries in MinBWs have been handled.
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unsigned NumProcessedRecipes = 0;
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#endif
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// Keep track of created truncates, so they can be re-used. Note that we
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// cannot use RAUW after creating a new truncate, as this would could make
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// other uses have different types for their operands, making them invalidly
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@@ -1659,38 +1654,12 @@ void VPlanTransforms::truncateToMinimalBitwidths(
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if (!NewResSizeInBits)
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continue;
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#ifndef NDEBUG
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NumProcessedRecipes++;
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#endif
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// If the value wasn't vectorized, we must maintain the original scalar
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// type. Skip those here, after incrementing NumProcessedRecipes. Also
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// skip casts which do not need to be handled explicitly here, as
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// redundant casts will be removed during recipe simplification.
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if (isa<VPReplicateRecipe, VPWidenCastRecipe>(&R)) {
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#ifndef NDEBUG
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// If any of the operands is a live-in and not used by VPWidenRecipe or
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// VPWidenSelectRecipe, but in MinBWs, make sure it is counted as
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// processed as well. When MinBWs is currently constructed, there is no
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// information about whether recipes are widened or replicated and in
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// case they are reciplicated the operands are not truncated. Counting
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// them them here ensures we do not miss any recipes in MinBWs.
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// TODO: Remove once the analysis is done on VPlan.
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for (VPValue *Op : R.operands()) {
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if (!Op->isLiveIn())
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continue;
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auto *UV = dyn_cast_or_null<Instruction>(Op->getUnderlyingValue());
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if (UV && MinBWs.contains(UV) && !ProcessedTruncs.contains(Op) &&
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none_of(Op->users(),
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IsaPred<VPWidenRecipe, VPWidenSelectRecipe>)) {
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// Add an entry to ProcessedTruncs to avoid counting the same
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// operand multiple times.
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ProcessedTruncs[Op] = nullptr;
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NumProcessedRecipes += 1;
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}
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}
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#endif
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if (isa<VPReplicateRecipe, VPWidenCastRecipe>(&R))
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continue;
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}
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Type *OldResTy = TypeInfo.inferScalarType(ResultVPV);
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unsigned OldResSizeInBits = OldResTy->getScalarSizeInBits();
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@@ -1749,19 +1718,11 @@ void VPlanTransforms::truncateToMinimalBitwidths(
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NewOp->insertBefore(&R);
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} else {
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PH->appendRecipe(NewOp);
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#ifndef NDEBUG
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auto *OpInst = dyn_cast<Instruction>(Op->getLiveInIRValue());
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bool IsContained = MinBWs.contains(OpInst);
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NumProcessedRecipes += IsContained;
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#endif
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}
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}
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}
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}
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assert(MinBWs.size() == NumProcessedRecipes &&
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"some entries in MinBWs haven't been processed");
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}
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/// Remove BranchOnCond recipes with true conditions together with removing
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58
llvm/test/Transforms/LoopVectorize/pr125278.ll
Normal file
58
llvm/test/Transforms/LoopVectorize/pr125278.ll
Normal file
@@ -0,0 +1,58 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
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define void @pr125278(ptr %dst, i64 %n) {
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; CHECK-LABEL: define void @pr125278(
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; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TRUE_EXT:%.*]] = zext i1 true to i32
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; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
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; CHECK-NEXT: br label %[[COND:.*]]
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; CHECK: [[COND_LOOPEXIT:.*]]:
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; CHECK-NEXT: br label %[[COND]]
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; CHECK: [[COND]]:
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: store i8 1, ptr [[DST]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP0]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[COND_LOOPEXIT]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[COND]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[FALSE_EXT:%.*]] = zext i1 false to i32
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; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[FALSE_EXT]], [[TRUE_EXT]]
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; CHECK-NEXT: [[XOR_TRUNC:%.*]] = trunc i32 [[XOR]] to i8
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; CHECK-NEXT: store i8 [[XOR_TRUNC]], ptr [[DST]], align 1
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[COND_LOOPEXIT]], !llvm.loop [[LOOP3:![0-9]+]]
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;
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entry:
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%true.ext = zext i1 true to i32
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br label %cond
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cond:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %cond ], [ %iv.next, %loop ]
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%false.ext = zext i1 false to i32
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%xor = xor i32 %false.ext, %true.ext
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%xor.trunc = trunc i32 %xor to i8
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store i8 %xor.trunc, ptr %dst, align 1
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%iv.next = add i64 %iv, 1
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%cmp = icmp ult i64 %iv.next, %n
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br i1 %cmp, label %loop, label %cond
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}
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