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[RISCV] Put REQUIRES: riscv-registered-target in the first line of the file. NFC.

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To be more consistent with other files.
This commit is contained in:
Jim Lin
2025-07-01 09:39:24 +08:00
parent 393a75ebb7
commit ce159d20e5
9 changed files with 9 additions and 9 deletions
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2
clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
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@@ -1,5 +1,5 @@
// RUN: %clang --target=riscv32 -mcpu=andes-a25 --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target
// RUN: %clang --target=riscv32 -mcpu=andes-a25 --print-enabled-extensions | FileCheck %s
// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:

2
clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
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@@ -1,5 +1,5 @@
// RUN: %clang --target=riscv32 -mcpu=andes-a45 --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target
// RUN: %clang --target=riscv32 -mcpu=andes-a45 --print-enabled-extensions | FileCheck %s
// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:

2
clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
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@@ -1,5 +1,5 @@
// RUN: %clang --target=riscv64 -mcpu=andes-ax25 --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target
// RUN: %clang --target=riscv64 -mcpu=andes-ax25 --print-enabled-extensions | FileCheck %s
// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:

2
clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
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@@ -1,5 +1,5 @@
// RUN: %clang --target=riscv64 -mcpu=andes-ax45 --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target
// RUN: %clang --target=riscv64 -mcpu=andes-ax45 --print-enabled-extensions | FileCheck %s
// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:

2
clang/test/Driver/print-enabled-extensions/riscv-andes-ax45mpv.c
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@@ -1,5 +1,5 @@
// RUN: %clang --target=riscv64 -mcpu=andes-ax45mpv --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target
// RUN: %clang --target=riscv64 -mcpu=andes-ax45mpv --print-enabled-extensions | FileCheck %s
// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:

2
clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
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@@ -1,5 +1,5 @@
// RUN: %clang --target=riscv32 -mcpu=andes-n45 --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target
// RUN: %clang --target=riscv32 -mcpu=andes-n45 --print-enabled-extensions | FileCheck %s
// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:

2
clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c
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@@ -1,5 +1,5 @@
// RUN: %clang --target=riscv64 -mcpu=andes-nx45 --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target
// RUN: %clang --target=riscv64 -mcpu=andes-nx45 --print-enabled-extensions | FileCheck %s
// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:

2
clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c
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@@ -1,5 +1,5 @@
// RUN: %clang --target=riscv64 -mcpu=sifive-p870 --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target
// RUN: %clang --target=riscv64 -mcpu=sifive-p870 --print-enabled-extensions | FileCheck %s
// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:

2
clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c
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@@ -1,5 +1,5 @@
// RUN: %clang --target=riscv64 -mcpu=sifive-x390 -menable-experimental-extensions --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target
// RUN: %clang --target=riscv64 -mcpu=sifive-x390 -menable-experimental-extensions --print-enabled-extensions | FileCheck %s
// CHECK: Name Version Description
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)