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[NFC][AMDGPU] Update tests to use autogened CHECKs (#140648)

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This commit is contained in:
Chinmay Deshpande
2025-05-19 19:47:40 -07:00
committed by GitHub
parent 755acb174a
commit e264cff6fd
5 changed files with 8119 additions and 521 deletions
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760
llvm/test/CodeGen/AMDGPU/fceil64.ll
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@@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s
@@ -9,36 +10,98 @@ declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone
declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
; FUNC-LABEL: {{^}}fceil_f64:
; CI: v_ceil_f64_e32
; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
; SI-DAG: s_addk_i32 [[SEXP]], 0xfc01
; SI-DAG: s_lshr_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], [[SEXP]]
; SI-DAG: s_andn2_b64
; SI-DAG: cmp_gt_i32
; SI-DAG: s_cselect_b32
; SI-DAG: s_cselect_b32
; SI-DAG: cmp_lt_i32
; SI-DAG: s_cselect_b32
; SI-DAG: s_cselect_b32
; SI-DAG: v_cmp_gt_f64_e64 [[FCMP:s[[0-9]+:[0-9]+]]]
; SI-DAG: v_cmp_lg_f64_e32 vcc
; SI-DAG: s_and_b64 [[AND1:s[[0-9]+:[0-9]+]]], [[FCMP]], vcc
; SI-DAG: s_and_b64 [[AND1]], [[AND1]], exec
; SI-DAG: s_cselect_b32 s{{[0-9]+}}, 0x3ff00000, 0
; SI: v_add_f64
; SI: s_endpgm
define amdgpu_kernel void @fceil_f64(ptr addrspace(1) %out, double %x) {
; SI-LABEL: fceil_f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, 0xfffff
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s8, s3, 0xb0014
; SI-NEXT: s_and_b32 s9, s3, 0x80000000
; SI-NEXT: s_addk_i32 s8, 0xfc01
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
; SI-NEXT: s_andn2_b64 s[4:5], s[2:3], s[4:5]
; SI-NEXT: s_cmp_lt_i32 s8, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: s_cmp_gt_i32 s8, 51
; SI-NEXT: s_cselect_b32 s9, s3, s5
; SI-NEXT: s_cselect_b32 s8, s2, s4
; SI-NEXT: v_cmp_gt_f64_e64 s[4:5], s[2:3], 0
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[0:1]
; SI-NEXT: s_and_b64 s[2:3], s[4:5], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: v_mov_b32_e32 v1, s2
; SI-NEXT: v_add_f64 v[0:1], s[8:9], v[0:1]
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
%y = call double @llvm.ceil.f64(double %x) nounwind readnone
store double %y, ptr addrspace(1) %out
ret void
}
; FUNC-LABEL: {{^}}fceil_v2f64:
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
define amdgpu_kernel void @fceil_v2f64(ptr addrspace(1) %out, <2 x double> %x) {
; SI-LABEL: fceil_v2f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s9, 0xfffff
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: s_mov_b32 s8, s2
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s10, s7, 0xb0014
; SI-NEXT: s_and_b32 s12, s7, 0x80000000
; SI-NEXT: s_add_i32 s13, s10, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[10:11], s[8:9], s13
; SI-NEXT: s_andn2_b64 s[10:11], s[6:7], s[10:11]
; SI-NEXT: s_cmp_lt_i32 s13, 0
; SI-NEXT: s_cselect_b32 s10, 0, s10
; SI-NEXT: s_cselect_b32 s11, s12, s11
; SI-NEXT: s_cmp_gt_i32 s13, 51
; SI-NEXT: s_cselect_b32 s11, s7, s11
; SI-NEXT: s_cselect_b32 s10, s6, s10
; SI-NEXT: v_cmp_gt_f64_e64 s[12:13], s[6:7], 0
; SI-NEXT: v_mov_b32_e32 v1, s10
; SI-NEXT: v_mov_b32_e32 v2, s11
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[6:7], v[1:2]
; SI-NEXT: s_and_b64 s[6:7], s[12:13], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s12, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s6, s5, 0xb0014
; SI-NEXT: s_and_b32 s13, s5, 0x80000000
; SI-NEXT: s_add_i32 s14, s6, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], s14
; SI-NEXT: s_andn2_b64 s[6:7], s[4:5], s[6:7]
; SI-NEXT: s_cmp_lt_i32 s14, 0
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s13, s7
; SI-NEXT: s_cmp_gt_i32 s14, 51
; SI-NEXT: s_cselect_b32 s7, s5, s7
; SI-NEXT: s_cselect_b32 s6, s4, s6
; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[4:5], 0
; SI-NEXT: v_mov_b32_e32 v1, s12
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: v_mov_b32_e32 v3, s7
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[2:3]
; SI-NEXT: s_and_b64 s[4:5], s[8:9], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
; SI-NEXT: v_add_f64 v[2:3], s[10:11], v[0:1]
; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: v_add_f64 v[0:1], s[6:7], v[0:1]
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
%y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone
store <2 x double> %y, ptr addrspace(1) %out
ret void
@@ -54,51 +117,640 @@ define amdgpu_kernel void @fceil_v2f64(ptr addrspace(1) %out, <2 x double> %x) {
; ret void
; }
; FUNC-LABEL: {{^}}fceil_v4f64:
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
define amdgpu_kernel void @fceil_v4f64(ptr addrspace(1) %out, <4 x double> %x) {
; SI-LABEL: fceil_v4f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x9
; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x11
; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s13, 0xfffff
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: s_mov_b32 s12, s10
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s18, s3, 0xb0014
; SI-NEXT: s_and_b32 s20, s3, 0x80000000
; SI-NEXT: v_cmp_gt_f64_e64 s[14:15], s[2:3], 0
; SI-NEXT: v_cmp_gt_f64_e64 s[16:17], s[0:1], 0
; SI-NEXT: s_add_i32 s21, s18, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[18:19], s[12:13], s21
; SI-NEXT: s_andn2_b64 s[18:19], s[2:3], s[18:19]
; SI-NEXT: s_cmp_lt_i32 s21, 0
; SI-NEXT: s_cselect_b32 s18, 0, s18
; SI-NEXT: s_cselect_b32 s19, s20, s19
; SI-NEXT: s_cmp_gt_i32 s21, 51
; SI-NEXT: s_cselect_b32 s19, s3, s19
; SI-NEXT: s_cselect_b32 s18, s2, s18
; SI-NEXT: v_cmp_gt_f64_e64 s[20:21], s[6:7], 0
; SI-NEXT: v_mov_b32_e32 v1, s18
; SI-NEXT: v_mov_b32_e32 v2, s19
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[1:2]
; SI-NEXT: s_and_b64 s[2:3], s[14:15], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s22, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s2, s1, 0xb0014
; SI-NEXT: s_and_b32 s14, s1, 0x80000000
; SI-NEXT: s_add_i32 s15, s2, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[12:13], s15
; SI-NEXT: s_andn2_b64 s[2:3], s[0:1], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s15, 0
; SI-NEXT: s_cselect_b32 s2, 0, s2
; SI-NEXT: s_cselect_b32 s3, s14, s3
; SI-NEXT: s_cmp_gt_i32 s15, 51
; SI-NEXT: s_cselect_b32 s3, s1, s3
; SI-NEXT: s_cselect_b32 s2, s0, s2
; SI-NEXT: v_cmp_gt_f64_e64 s[14:15], s[4:5], 0
; SI-NEXT: v_mov_b32_e32 v1, s22
; SI-NEXT: v_mov_b32_e32 v2, s2
; SI-NEXT: v_mov_b32_e32 v3, s3
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[0:1], v[2:3]
; SI-NEXT: s_and_b64 s[0:1], s[16:17], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s16, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s0, s7, 0xb0014
; SI-NEXT: s_and_b32 s17, s7, 0x80000000
; SI-NEXT: s_add_i32 s22, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[12:13], s22
; SI-NEXT: s_andn2_b64 s[0:1], s[6:7], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s22, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s17, s1
; SI-NEXT: s_cmp_gt_i32 s22, 51
; SI-NEXT: s_cselect_b32 s1, s7, s1
; SI-NEXT: s_cselect_b32 s0, s6, s0
; SI-NEXT: v_add_f64 v[4:5], s[18:19], v[0:1]
; SI-NEXT: v_mov_b32_e32 v1, s16
; SI-NEXT: v_mov_b32_e32 v3, s1
; SI-NEXT: v_mov_b32_e32 v2, s0
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[6:7], v[2:3]
; SI-NEXT: s_and_b64 s[6:7], s[20:21], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s16, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s6, s5, 0xb0014
; SI-NEXT: s_and_b32 s17, s5, 0x80000000
; SI-NEXT: s_add_i32 s18, s6, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[6:7], s[12:13], s18
; SI-NEXT: s_andn2_b64 s[6:7], s[4:5], s[6:7]
; SI-NEXT: s_cmp_lt_i32 s18, 0
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s17, s7
; SI-NEXT: s_cmp_gt_i32 s18, 51
; SI-NEXT: s_cselect_b32 s7, s5, s7
; SI-NEXT: s_cselect_b32 s6, s4, s6
; SI-NEXT: v_add_f64 v[2:3], s[2:3], v[0:1]
; SI-NEXT: v_mov_b32_e32 v1, s16
; SI-NEXT: v_mov_b32_e32 v6, s6
; SI-NEXT: v_mov_b32_e32 v7, s7
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[6:7]
; SI-NEXT: s_and_b64 s[2:3], s[14:15], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
; SI-NEXT: v_add_f64 v[8:9], s[0:1], v[0:1]
; SI-NEXT: v_mov_b32_e32 v1, s2
; SI-NEXT: v_add_f64 v[6:7], s[6:7], v[0:1]
; SI-NEXT: buffer_store_dwordx4 v[6:9], off, s[8:11], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[2:5], off, s[8:11], 0
; SI-NEXT: s_endpgm
%y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
store <4 x double> %y, ptr addrspace(1) %out
ret void
}
; FUNC-LABEL: {{^}}fceil_v8f64:
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
define amdgpu_kernel void @fceil_v8f64(ptr addrspace(1) %out, <8 x double> %x) {
; SI-LABEL: fceil_v8f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x9
; SI-NEXT: s_load_dwordx16 s[0:15], s[4:5], 0x19
; SI-NEXT: s_mov_b32 s19, 0xf000
; SI-NEXT: s_mov_b32 s18, -1
; SI-NEXT: s_mov_b32 s21, 0xfffff
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: s_mov_b32 s20, s18
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s33, s3, 0xb0014
; SI-NEXT: s_and_b32 s40, s3, 0x80000000
; SI-NEXT: v_cmp_gt_f64_e64 s[22:23], s[2:3], 0
; SI-NEXT: v_cmp_gt_f64_e64 s[26:27], s[0:1], 0
; SI-NEXT: v_cmp_gt_f64_e64 s[30:31], s[6:7], 0
; SI-NEXT: v_cmp_gt_f64_e64 s[36:37], s[4:5], 0
; SI-NEXT: v_cmp_gt_f64_e64 s[24:25], s[10:11], 0
; SI-NEXT: v_cmp_gt_f64_e64 s[28:29], s[8:9], 0
; SI-NEXT: v_cmp_gt_f64_e64 s[34:35], s[14:15], 0
; SI-NEXT: s_addk_i32 s33, 0xfc01
; SI-NEXT: s_lshr_b64 s[38:39], s[20:21], s33
; SI-NEXT: s_andn2_b64 s[38:39], s[2:3], s[38:39]
; SI-NEXT: s_cmp_lt_i32 s33, 0
; SI-NEXT: s_cselect_b32 s38, 0, s38
; SI-NEXT: s_cselect_b32 s39, s40, s39
; SI-NEXT: s_cmp_gt_i32 s33, 51
; SI-NEXT: s_cselect_b32 s41, s3, s39
; SI-NEXT: s_cselect_b32 s40, s2, s38
; SI-NEXT: v_cmp_gt_f64_e64 s[38:39], s[12:13], 0
; SI-NEXT: v_mov_b32_e32 v0, s40
; SI-NEXT: v_mov_b32_e32 v1, s41
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[0:1]
; SI-NEXT: s_and_b64 s[2:3], s[22:23], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s3, s1, 0xb0014
; SI-NEXT: s_and_b32 s22, s1, 0x80000000
; SI-NEXT: v_mov_b32_e32 v5, s2
; SI-NEXT: s_add_i32 s23, s3, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[20:21], s23
; SI-NEXT: s_andn2_b64 s[2:3], s[0:1], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s23, 0
; SI-NEXT: s_cselect_b32 s2, 0, s2
; SI-NEXT: s_cselect_b32 s3, s22, s3
; SI-NEXT: s_cmp_gt_i32 s23, 51
; SI-NEXT: s_cselect_b32 s3, s1, s3
; SI-NEXT: s_cselect_b32 s2, s0, s2
; SI-NEXT: v_add_f64 v[2:3], s[40:41], v[4:5]
; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[0:1], v[0:1]
; SI-NEXT: s_and_b64 s[0:1], s[26:27], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s1, s7, 0xb0014
; SI-NEXT: s_and_b32 s22, s7, 0x80000000
; SI-NEXT: v_mov_b32_e32 v5, s0
; SI-NEXT: s_add_i32 s23, s1, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[20:21], s23
; SI-NEXT: s_andn2_b64 s[0:1], s[6:7], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s23, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s22, s1
; SI-NEXT: s_cmp_gt_i32 s23, 51
; SI-NEXT: s_cselect_b32 s1, s7, s1
; SI-NEXT: s_cselect_b32 s0, s6, s0
; SI-NEXT: v_add_f64 v[0:1], s[2:3], v[4:5]
; SI-NEXT: v_mov_b32_e32 v6, s1
; SI-NEXT: v_mov_b32_e32 v5, s0
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[6:7], v[5:6]
; SI-NEXT: s_and_b64 s[2:3], s[30:31], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s3, s5, 0xb0014
; SI-NEXT: s_and_b32 s6, s5, 0x80000000
; SI-NEXT: v_mov_b32_e32 v5, s2
; SI-NEXT: s_add_i32 s7, s3, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[20:21], s7
; SI-NEXT: s_andn2_b64 s[2:3], s[4:5], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s7, 0
; SI-NEXT: s_cselect_b32 s2, 0, s2
; SI-NEXT: s_cselect_b32 s3, s6, s3
; SI-NEXT: s_cmp_gt_i32 s7, 51
; SI-NEXT: s_cselect_b32 s3, s5, s3
; SI-NEXT: s_cselect_b32 s2, s4, s2
; SI-NEXT: v_add_f64 v[7:8], s[0:1], v[4:5]
; SI-NEXT: v_mov_b32_e32 v6, s3
; SI-NEXT: v_mov_b32_e32 v5, s2
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[5:6]
; SI-NEXT: s_and_b64 s[0:1], s[36:37], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s1, s11, 0xb0014
; SI-NEXT: s_and_b32 s4, s11, 0x80000000
; SI-NEXT: v_mov_b32_e32 v5, s0
; SI-NEXT: v_add_f64 v[5:6], s[2:3], v[4:5]
; SI-NEXT: s_add_i32 s2, s1, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[20:21], s2
; SI-NEXT: s_andn2_b64 s[0:1], s[10:11], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s2, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s4, s1
; SI-NEXT: s_cmp_gt_i32 s2, 51
; SI-NEXT: s_cselect_b32 s1, s11, s1
; SI-NEXT: s_cselect_b32 s0, s10, s0
; SI-NEXT: buffer_store_dwordx4 v[5:8], off, s[16:19], 0 offset:16
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v6, s1
; SI-NEXT: v_mov_b32_e32 v5, s0
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[5:6]
; SI-NEXT: s_and_b64 s[2:3], s[24:25], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s3, s9, 0xb0014
; SI-NEXT: s_and_b32 s4, s9, 0x80000000
; SI-NEXT: v_mov_b32_e32 v5, s2
; SI-NEXT: s_add_i32 s5, s3, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[20:21], s5
; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s5, 0
; SI-NEXT: s_cselect_b32 s2, 0, s2
; SI-NEXT: s_cselect_b32 s3, s4, s3
; SI-NEXT: s_cmp_gt_i32 s5, 51
; SI-NEXT: s_cselect_b32 s3, s9, s3
; SI-NEXT: s_cselect_b32 s2, s8, s2
; SI-NEXT: v_add_f64 v[7:8], s[0:1], v[4:5]
; SI-NEXT: v_mov_b32_e32 v6, s3
; SI-NEXT: v_mov_b32_e32 v5, s2
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[5:6]
; SI-NEXT: s_and_b64 s[0:1], s[28:29], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s1, s15, 0xb0014
; SI-NEXT: s_and_b32 s4, s15, 0x80000000
; SI-NEXT: v_mov_b32_e32 v5, s0
; SI-NEXT: s_add_i32 s5, s1, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[20:21], s5
; SI-NEXT: s_andn2_b64 s[0:1], s[14:15], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s5, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s4, s1
; SI-NEXT: s_cmp_gt_i32 s5, 51
; SI-NEXT: s_cselect_b32 s1, s15, s1
; SI-NEXT: s_cselect_b32 s0, s14, s0
; SI-NEXT: v_add_f64 v[5:6], s[2:3], v[4:5]
; SI-NEXT: v_mov_b32_e32 v10, s1
; SI-NEXT: v_mov_b32_e32 v9, s0
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[9:10]
; SI-NEXT: s_and_b64 s[2:3], s[34:35], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s2, s13, 0xb0014
; SI-NEXT: s_and_b32 s5, s13, 0x80000000
; SI-NEXT: s_add_i32 s6, s2, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[20:21], s6
; SI-NEXT: s_andn2_b64 s[2:3], s[12:13], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s6, 0
; SI-NEXT: s_cselect_b32 s2, 0, s2
; SI-NEXT: s_cselect_b32 s3, s5, s3
; SI-NEXT: s_cmp_gt_i32 s6, 51
; SI-NEXT: s_cselect_b32 s3, s13, s3
; SI-NEXT: s_cselect_b32 s2, s12, s2
; SI-NEXT: buffer_store_dwordx4 v[5:8], off, s[16:19], 0 offset:32
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, s4
; SI-NEXT: v_mov_b32_e32 v7, s3
; SI-NEXT: v_mov_b32_e32 v6, s2
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[6:7]
; SI-NEXT: s_and_b64 s[4:5], s[38:39], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
; SI-NEXT: v_add_f64 v[6:7], s[0:1], v[4:5]
; SI-NEXT: v_mov_b32_e32 v5, s4
; SI-NEXT: v_add_f64 v[4:5], s[2:3], v[4:5]
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 offset:48
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
; SI-NEXT: s_endpgm
%y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone
store <8 x double> %y, ptr addrspace(1) %out
ret void
}
; FUNC-LABEL: {{^}}fceil_v16f64:
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
; CI: v_ceil_f64_e32
define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x) {
; SI-LABEL: fceil_v16f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x29
; SI-NEXT: s_mov_b32 s26, -1
; SI-NEXT: s_mov_b32 s29, 0xfffff
; SI-NEXT: s_load_dwordx2 s[24:25], s[4:5], 0x9
; SI-NEXT: v_mov_b32_e32 v8, 0
; SI-NEXT: s_mov_b32 s28, s26
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
; SI-NEXT: s_and_b32 s2, s11, 0x80000000
; SI-NEXT: s_add_i32 s3, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s3
; SI-NEXT: s_andn2_b64 s[0:1], s[10:11], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s2, s1
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s3, s11, s1
; SI-NEXT: s_cselect_b32 s2, s10, s0
; SI-NEXT: v_cmp_gt_f64_e64 s[0:1], s[10:11], 0
; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]
; SI-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s10, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014
; SI-NEXT: s_and_b32 s6, s9, 0x80000000
; SI-NEXT: s_add_i32 s7, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s7
; SI-NEXT: s_andn2_b64 s[0:1], s[8:9], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s7, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s6, s1
; SI-NEXT: s_cmp_gt_i32 s7, 51
; SI-NEXT: s_cselect_b32 s7, s9, s1
; SI-NEXT: s_cselect_b32 s6, s8, s0
; SI-NEXT: v_cmp_gt_f64_e64 s[0:1], s[8:9], 0
; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[0:1]
; SI-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s27, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s0, s15, 0xb0014
; SI-NEXT: s_and_b32 s8, s15, 0x80000000
; SI-NEXT: s_add_i32 s9, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s9
; SI-NEXT: s_andn2_b64 s[0:1], s[14:15], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s9, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s8, s1
; SI-NEXT: s_cmp_gt_i32 s9, 51
; SI-NEXT: s_cselect_b32 s9, s15, s1
; SI-NEXT: s_cselect_b32 s8, s14, s0
; SI-NEXT: v_cmp_gt_f64_e64 s[0:1], s[14:15], 0
; SI-NEXT: v_mov_b32_e32 v9, s10
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[0:1]
; SI-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s14, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s0, s13, 0xb0014
; SI-NEXT: s_and_b32 s10, s13, 0x80000000
; SI-NEXT: s_add_i32 s15, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s15
; SI-NEXT: s_andn2_b64 s[0:1], s[12:13], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s15, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s10, s1
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[12:13], 0
; SI-NEXT: s_cmp_gt_i32 s15, 51
; SI-NEXT: s_cselect_b32 s1, s13, s1
; SI-NEXT: s_cselect_b32 s0, s12, s0
; SI-NEXT: v_add_f64 v[2:3], s[2:3], v[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s27
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[0:1]
; SI-NEXT: s_and_b64 s[2:3], s[10:11], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s10, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s2, s19, 0xb0014
; SI-NEXT: s_and_b32 s11, s19, 0x80000000
; SI-NEXT: s_add_i32 s12, s2, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s12
; SI-NEXT: s_andn2_b64 s[2:3], s[18:19], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s12, 0
; SI-NEXT: s_cselect_b32 s13, 0, s2
; SI-NEXT: s_cselect_b32 s11, s11, s3
; SI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[18:19], 0
; SI-NEXT: s_cmp_gt_i32 s12, 51
; SI-NEXT: s_cselect_b32 s31, s19, s11
; SI-NEXT: s_cselect_b32 s30, s18, s13
; SI-NEXT: v_add_f64 v[0:1], s[6:7], v[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s14
; SI-NEXT: v_mov_b32_e32 v4, s30
; SI-NEXT: v_mov_b32_e32 v5, s31
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[18:19], v[4:5]
; SI-NEXT: s_and_b64 s[2:3], s[2:3], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s33, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s2, s17, 0xb0014
; SI-NEXT: s_and_b32 s6, s17, 0x80000000
; SI-NEXT: s_add_i32 s7, s2, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s7
; SI-NEXT: s_andn2_b64 s[2:3], s[16:17], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s7, 0
; SI-NEXT: s_cselect_b32 s11, 0, s2
; SI-NEXT: s_cselect_b32 s6, s6, s3
; SI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[16:17], 0
; SI-NEXT: s_cmp_gt_i32 s7, 51
; SI-NEXT: s_cselect_b32 s19, s17, s6
; SI-NEXT: s_cselect_b32 s18, s16, s11
; SI-NEXT: v_add_f64 v[6:7], s[8:9], v[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s10
; SI-NEXT: v_mov_b32_e32 v4, s18
; SI-NEXT: v_mov_b32_e32 v5, s19
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[16:17], v[4:5]
; SI-NEXT: s_and_b64 s[2:3], s[2:3], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s36, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s2, s23, 0xb0014
; SI-NEXT: s_and_b32 s6, s23, 0x80000000
; SI-NEXT: s_add_i32 s7, s2, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s7
; SI-NEXT: s_andn2_b64 s[2:3], s[22:23], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s7, 0
; SI-NEXT: s_cselect_b32 s6, s6, s3
; SI-NEXT: s_cselect_b32 s8, 0, s2
; SI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[22:23], 0
; SI-NEXT: s_cmp_gt_i32 s7, 51
; SI-NEXT: s_cselect_b32 s35, s23, s6
; SI-NEXT: s_cselect_b32 s34, s22, s8
; SI-NEXT: v_add_f64 v[4:5], s[0:1], v[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s34
; SI-NEXT: v_mov_b32_e32 v10, s35
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[22:23], v[9:10]
; SI-NEXT: s_and_b64 s[0:1], s[2:3], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s37, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s0, s21, 0xb0014
; SI-NEXT: s_and_b32 s2, s21, 0x80000000
; SI-NEXT: s_add_i32 s3, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s3
; SI-NEXT: s_andn2_b64 s[0:1], s[20:21], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s1, s2, s1
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s17, s21, s1
; SI-NEXT: s_cselect_b32 s16, s20, s0
; SI-NEXT: v_cmp_gt_f64_e64 s[22:23], s[20:21], 0
; SI-NEXT: v_mov_b32_e32 v9, s16
; SI-NEXT: v_mov_b32_e32 v10, s17
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[20:21], v[9:10]
; SI-NEXT: s_load_dwordx16 s[0:15], s[4:5], 0x39
; SI-NEXT: s_mov_b32 s27, 0xf000
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:16
; SI-NEXT: v_mov_b32_e32 v9, s33
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_f64 v[6:7], s[30:31], v[8:9]
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cmp_gt_f64_e64 s[20:21], s[2:3], 0
; SI-NEXT: v_mov_b32_e32 v9, s36
; SI-NEXT: v_cmp_gt_f64_e64 s[30:31], s[0:1], 0
; SI-NEXT: v_add_f64 v[4:5], s[18:19], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 s[18:19], s[6:7], 0
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:32
; SI-NEXT: v_mov_b32_e32 v9, s37
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_f64 v[6:7], s[34:35], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 s[34:35], s[4:5], 0
; SI-NEXT: s_and_b64 s[22:23], s[22:23], vcc
; SI-NEXT: s_and_b64 s[22:23], s[22:23], exec
; SI-NEXT: s_cselect_b32 s22, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s23, s3, 0xb0014
; SI-NEXT: s_and_b32 s33, s3, 0x80000000
; SI-NEXT: v_mov_b32_e32 v9, s22
; SI-NEXT: s_add_i32 s36, s23, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[22:23], s[28:29], s36
; SI-NEXT: s_andn2_b64 s[22:23], s[2:3], s[22:23]
; SI-NEXT: s_cmp_lt_i32 s36, 0
; SI-NEXT: s_cselect_b32 s38, 0, s22
; SI-NEXT: s_cselect_b32 s33, s33, s23
; SI-NEXT: v_cmp_gt_f64_e64 s[22:23], s[10:11], 0
; SI-NEXT: s_cmp_gt_i32 s36, 51
; SI-NEXT: s_cselect_b32 s37, s3, s33
; SI-NEXT: s_cselect_b32 s36, s2, s38
; SI-NEXT: v_add_f64 v[4:5], s[16:17], v[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s36
; SI-NEXT: v_mov_b32_e32 v10, s37
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[9:10]
; SI-NEXT: s_and_b64 s[2:3], s[20:21], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s3, s1, 0xb0014
; SI-NEXT: s_and_b32 s16, s1, 0x80000000
; SI-NEXT: v_mov_b32_e32 v9, s2
; SI-NEXT: s_add_i32 s17, s3, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s17
; SI-NEXT: s_andn2_b64 s[2:3], s[0:1], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s17, 0
; SI-NEXT: s_cselect_b32 s20, 0, s2
; SI-NEXT: s_cselect_b32 s16, s16, s3
; SI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[8:9], 0
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:48
; SI-NEXT: s_cmp_gt_i32 s17, 51
; SI-NEXT: s_cselect_b32 s17, s1, s16
; SI-NEXT: s_cselect_b32 s16, s0, s20
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_f64 v[6:7], s[36:37], v[8:9]
; SI-NEXT: v_mov_b32_e32 v4, s16
; SI-NEXT: v_mov_b32_e32 v5, s17
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[0:1], v[4:5]
; SI-NEXT: s_and_b64 s[0:1], s[30:31], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s1, s7, 0xb0014
; SI-NEXT: s_and_b32 s20, s7, 0x80000000
; SI-NEXT: v_mov_b32_e32 v9, s0
; SI-NEXT: s_add_i32 s21, s1, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s21
; SI-NEXT: s_andn2_b64 s[0:1], s[6:7], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s21, 0
; SI-NEXT: s_cselect_b32 s30, 0, s0
; SI-NEXT: s_cselect_b32 s20, s20, s1
; SI-NEXT: v_cmp_gt_f64_e64 s[0:1], s[14:15], 0
; SI-NEXT: s_cmp_gt_i32 s21, 51
; SI-NEXT: s_cselect_b32 s21, s7, s20
; SI-NEXT: s_cselect_b32 s20, s6, s30
; SI-NEXT: v_add_f64 v[4:5], s[16:17], v[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s20
; SI-NEXT: v_mov_b32_e32 v10, s21
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[6:7], v[9:10]
; SI-NEXT: s_and_b64 s[6:7], s[18:19], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s6, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s7, s5, 0xb0014
; SI-NEXT: s_and_b32 s16, s5, 0x80000000
; SI-NEXT: v_mov_b32_e32 v9, s6
; SI-NEXT: s_add_i32 s17, s7, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[6:7], s[28:29], s17
; SI-NEXT: s_andn2_b64 s[6:7], s[4:5], s[6:7]
; SI-NEXT: s_cmp_lt_i32 s17, 0
; SI-NEXT: s_cselect_b32 s18, 0, s6
; SI-NEXT: s_cselect_b32 s16, s16, s7
; SI-NEXT: v_cmp_gt_f64_e64 s[6:7], s[12:13], 0
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:64
; SI-NEXT: s_cmp_gt_i32 s17, 51
; SI-NEXT: s_cselect_b32 s17, s5, s16
; SI-NEXT: s_cselect_b32 s16, s4, s18
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_f64 v[6:7], s[20:21], v[8:9]
; SI-NEXT: v_mov_b32_e32 v4, s16
; SI-NEXT: v_mov_b32_e32 v5, s17
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[4:5]
; SI-NEXT: s_and_b64 s[4:5], s[34:35], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s5, s11, 0xb0014
; SI-NEXT: s_and_b32 s18, s11, 0x80000000
; SI-NEXT: v_mov_b32_e32 v9, s4
; SI-NEXT: v_add_f64 v[4:5], s[16:17], v[8:9]
; SI-NEXT: s_add_i32 s16, s5, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[4:5], s[28:29], s16
; SI-NEXT: s_andn2_b64 s[4:5], s[10:11], s[4:5]
; SI-NEXT: s_cmp_lt_i32 s16, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s18, s5
; SI-NEXT: s_cmp_gt_i32 s16, 51
; SI-NEXT: s_cselect_b32 s5, s11, s5
; SI-NEXT: s_cselect_b32 s4, s10, s4
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:80
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: v_mov_b32_e32 v5, s5
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[4:5]
; SI-NEXT: s_and_b64 s[10:11], s[22:23], vcc
; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec
; SI-NEXT: s_cselect_b32 s10, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s11, s9, 0xb0014
; SI-NEXT: s_and_b32 s16, s9, 0x80000000
; SI-NEXT: v_mov_b32_e32 v9, s10
; SI-NEXT: s_add_i32 s17, s11, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[10:11], s[28:29], s17
; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[10:11]
; SI-NEXT: s_cmp_lt_i32 s17, 0
; SI-NEXT: s_cselect_b32 s10, 0, s10
; SI-NEXT: s_cselect_b32 s11, s16, s11
; SI-NEXT: s_cmp_gt_i32 s17, 51
; SI-NEXT: s_cselect_b32 s11, s9, s11
; SI-NEXT: s_cselect_b32 s10, s8, s10
; SI-NEXT: v_add_f64 v[6:7], s[4:5], v[8:9]
; SI-NEXT: v_mov_b32_e32 v4, s10
; SI-NEXT: v_mov_b32_e32 v5, s11
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[4:5]
; SI-NEXT: s_and_b64 s[2:3], s[2:3], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s3, s15, 0xb0014
; SI-NEXT: s_and_b32 s4, s15, 0x80000000
; SI-NEXT: v_mov_b32_e32 v9, s2
; SI-NEXT: s_add_i32 s5, s3, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s5
; SI-NEXT: s_andn2_b64 s[2:3], s[14:15], s[2:3]
; SI-NEXT: s_cmp_lt_i32 s5, 0
; SI-NEXT: s_cselect_b32 s2, 0, s2
; SI-NEXT: s_cselect_b32 s3, s4, s3
; SI-NEXT: s_cmp_gt_i32 s5, 51
; SI-NEXT: s_cselect_b32 s3, s15, s3
; SI-NEXT: s_cselect_b32 s2, s14, s2
; SI-NEXT: v_add_f64 v[4:5], s[10:11], v[8:9]
; SI-NEXT: v_mov_b32_e32 v10, s3
; SI-NEXT: v_mov_b32_e32 v9, s2
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[9:10]
; SI-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s0, s13, 0xb0014
; SI-NEXT: s_and_b32 s5, s13, 0x80000000
; SI-NEXT: s_add_i32 s8, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s8
; SI-NEXT: s_andn2_b64 s[0:1], s[12:13], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s8, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s5, s1
; SI-NEXT: s_cmp_gt_i32 s8, 51
; SI-NEXT: s_cselect_b32 s1, s13, s1
; SI-NEXT: s_cselect_b32 s0, s12, s0
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:96
; SI-NEXT: v_mov_b32_e32 v9, s4
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, s1
; SI-NEXT: v_mov_b32_e32 v4, s0
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[4:5]
; SI-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0
; SI-NEXT: v_add_f64 v[6:7], s[2:3], v[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s4
; SI-NEXT: v_add_f64 v[4:5], s[0:1], v[8:9]
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:112
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[24:27], 0
; SI-NEXT: s_endpgm
%y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone
store <16 x double> %y, ptr addrspace(1) %out
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CI: {{.*}}
; FUNC: {{.*}}

138
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
View File

@@ -1,75 +1,117 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,UNPACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED %s
; GCN-LABEL: {{^}}buffer_store_format_d16_x:
; GCN: s_load_dword s[[LO:[0-9]+]]
; GCN: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[LO]]
; GCN: buffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_x(<4 x i32> %rsrc, [8 x i32], half %data, [8 x i32], i32 %voffset) {
; GCN-LABEL: buffer_store_format_d16_x:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_load_dword s4, s[8:9], 0x30
; GCN-NEXT: s_load_dword s5, s[8:9], 0x54
; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: buffer_store_format_d16_x v0, v1, s[0:3], 0 offen
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.format.f16(half %data, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_d16_xy:
; UNPACKED: s_load_dwordx2 s[[[S_DATA:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], s[[S_DATA]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], s[[S_DATA]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
; UNPACKED: buffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %voffset) {
; UNPACKED-LABEL: buffer_store_format_d16_xy:
; UNPACKED: ; %bb.0: ; %main_body
; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; UNPACKED-NEXT: s_lshr_b32 s6, s4, 16
; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
; UNPACKED-NEXT: v_mov_b32_e32 v1, s6
; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; UNPACKED-NEXT: buffer_store_format_d16_xy v[0:1], v2, s[0:3], 0 offen
; UNPACKED-NEXT: s_endpgm
;
; PACKED-LABEL: buffer_store_format_d16_xy:
; PACKED: ; %bb.0: ; %main_body
; PACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; PACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-NEXT: v_mov_b32_e32 v0, s4
; PACKED-NEXT: v_mov_b32_e32 v1, s5
; PACKED-NEXT: buffer_store_format_d16_xy v0, v1, s[0:3], 0 offen
; PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_d16_xyz:
; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
; UNPACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
; PACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_xyz(<4 x i32> %rsrc, <4 x half> %data, i32 %voffset) {
; UNPACKED-LABEL: buffer_store_format_d16_xyz:
; UNPACKED: ; %bb.0: ; %main_body
; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; UNPACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
; UNPACKED-NEXT: s_lshr_b32 s7, s4, 16
; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
; UNPACKED-NEXT: v_mov_b32_e32 v1, s7
; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; UNPACKED-NEXT: v_mov_b32_e32 v3, s6
; UNPACKED-NEXT: buffer_store_format_d16_xyz v[0:2], v3, s[0:3], 0 offen
; UNPACKED-NEXT: s_endpgm
;
; PACKED-LABEL: buffer_store_format_d16_xyz:
; PACKED: ; %bb.0: ; %main_body
; PACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; PACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; PACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-NEXT: s_and_b32 s5, s5, 0xffff
; PACKED-NEXT: v_mov_b32_e32 v0, s4
; PACKED-NEXT: v_mov_b32_e32 v1, s5
; PACKED-NEXT: v_mov_b32_e32 v2, s6
; PACKED-NEXT: buffer_store_format_d16_xyz v[0:1], v2, s[0:3], 0 offen
; PACKED-NEXT: s_endpgm
main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> poison, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.raw.buffer.store.format.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw:
; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; UNPACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
; PACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %voffset) {
; UNPACKED-LABEL: buffer_store_format_d16_xyzw:
; UNPACKED: ; %bb.0: ; %main_body
; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; UNPACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; UNPACKED-NEXT: s_lshr_b32 s7, s5, 16
; UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
; UNPACKED-NEXT: s_lshr_b32 s8, s4, 16
; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
; UNPACKED-NEXT: v_mov_b32_e32 v1, s8
; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; UNPACKED-NEXT: v_mov_b32_e32 v3, s7
; UNPACKED-NEXT: v_mov_b32_e32 v4, s6
; UNPACKED-NEXT: buffer_store_format_d16_xyzw v[0:3], v4, s[0:3], 0 offen
; UNPACKED-NEXT: s_endpgm
;
; PACKED-LABEL: buffer_store_format_d16_xyzw:
; PACKED: ; %bb.0: ; %main_body
; PACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; PACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; PACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-NEXT: v_mov_b32_e32 v0, s4
; PACKED-NEXT: v_mov_b32_e32 v1, s5
; PACKED-NEXT: v_mov_b32_e32 v2, s6
; PACKED-NEXT: buffer_store_format_d16_xyzw v[0:1], v2, s[0:3], 0 offen
; PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
ret void

138
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
View File

@@ -1,75 +1,117 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,UNPACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED %s
; GCN-LABEL: {{^}}buffer_store_format_d16_x:
; GCN: s_load_dword s[[LO:[0-9]+]]
; GCN: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[LO]]
; GCN: buffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_x(ptr addrspace(8) %rsrc, [8 x i32], half %data, [8 x i32], i32 %voffset) {
; GCN-LABEL: buffer_store_format_d16_x:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_load_dword s4, s[8:9], 0x30
; GCN-NEXT: s_load_dword s5, s[8:9], 0x54
; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: buffer_store_format_d16_x v0, v1, s[0:3], 0 offen
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.store.format.f16(half %data, ptr addrspace(8) %rsrc, i32 %voffset, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_d16_xy:
; UNPACKED: s_load_dwordx2 s[[[S_DATA:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], s[[S_DATA]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], s[[S_DATA]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
; UNPACKED: buffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_xy(ptr addrspace(8) %rsrc, <2 x half> %data, i32 %voffset) {
; UNPACKED-LABEL: buffer_store_format_d16_xy:
; UNPACKED: ; %bb.0: ; %main_body
; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; UNPACKED-NEXT: s_lshr_b32 s6, s4, 16
; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
; UNPACKED-NEXT: v_mov_b32_e32 v1, s6
; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; UNPACKED-NEXT: buffer_store_format_d16_xy v[0:1], v2, s[0:3], 0 offen
; UNPACKED-NEXT: s_endpgm
;
; PACKED-LABEL: buffer_store_format_d16_xy:
; PACKED: ; %bb.0: ; %main_body
; PACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; PACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-NEXT: v_mov_b32_e32 v0, s4
; PACKED-NEXT: v_mov_b32_e32 v1, s5
; PACKED-NEXT: buffer_store_format_d16_xy v0, v1, s[0:3], 0 offen
; PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.store.format.v2f16(<2 x half> %data, ptr addrspace(8) %rsrc, i32 %voffset, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_d16_xyz:
; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
; UNPACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
; PACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_xyz(ptr addrspace(8) %rsrc, <4 x half> %data, i32 %voffset) {
; UNPACKED-LABEL: buffer_store_format_d16_xyz:
; UNPACKED: ; %bb.0: ; %main_body
; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; UNPACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
; UNPACKED-NEXT: s_lshr_b32 s7, s4, 16
; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
; UNPACKED-NEXT: v_mov_b32_e32 v1, s7
; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; UNPACKED-NEXT: v_mov_b32_e32 v3, s6
; UNPACKED-NEXT: buffer_store_format_d16_xyz v[0:2], v3, s[0:3], 0 offen
; UNPACKED-NEXT: s_endpgm
;
; PACKED-LABEL: buffer_store_format_d16_xyz:
; PACKED: ; %bb.0: ; %main_body
; PACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; PACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; PACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-NEXT: s_and_b32 s5, s5, 0xffff
; PACKED-NEXT: v_mov_b32_e32 v0, s4
; PACKED-NEXT: v_mov_b32_e32 v1, s5
; PACKED-NEXT: v_mov_b32_e32 v2, s6
; PACKED-NEXT: buffer_store_format_d16_xyz v[0:1], v2, s[0:3], 0 offen
; PACKED-NEXT: s_endpgm
main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> poison, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.raw.ptr.buffer.store.format.v3f16(<3 x half> %data_subvec, ptr addrspace(8) %rsrc, i32 %voffset, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw:
; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; UNPACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
; PACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_xyzw(ptr addrspace(8) %rsrc, <4 x half> %data, i32 %voffset) {
; UNPACKED-LABEL: buffer_store_format_d16_xyzw:
; UNPACKED: ; %bb.0: ; %main_body
; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; UNPACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; UNPACKED-NEXT: s_lshr_b32 s7, s5, 16
; UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
; UNPACKED-NEXT: s_lshr_b32 s8, s4, 16
; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
; UNPACKED-NEXT: v_mov_b32_e32 v1, s8
; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; UNPACKED-NEXT: v_mov_b32_e32 v3, s7
; UNPACKED-NEXT: v_mov_b32_e32 v4, s6
; UNPACKED-NEXT: buffer_store_format_d16_xyzw v[0:3], v4, s[0:3], 0 offen
; UNPACKED-NEXT: s_endpgm
;
; PACKED-LABEL: buffer_store_format_d16_xyzw:
; PACKED: ; %bb.0: ; %main_body
; PACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; PACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; PACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-NEXT: v_mov_b32_e32 v0, s4
; PACKED-NEXT: v_mov_b32_e32 v1, s5
; PACKED-NEXT: v_mov_b32_e32 v2, s6
; PACKED-NEXT: buffer_store_format_d16_xyzw v[0:1], v2, s[0:3], 0 offen
; PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.store.format.v4f16(<4 x half> %data, ptr addrspace(8) %rsrc, i32 %voffset, i32 0, i32 0)
ret void

152
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
View File

@@ -1,85 +1,133 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,UNPACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED %s
; GCN-LABEL: {{^}}buffer_store_format_d16_x:
; GCN: s_load_dword s[[LO:[0-9]+]]
; GCN: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[LO]]
; GCN: buffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_x(<4 x i32> %rsrc, [8 x i32], half %data, [8 x i32], i32 %index) {
; GCN-LABEL: buffer_store_format_d16_x:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_load_dword s4, s[8:9], 0x30
; GCN-NEXT: s_load_dword s5, s[8:9], 0x54
; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: buffer_store_format_d16_x v0, v1, s[0:3], 0 idxen
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.buffer.store.format.f16(half %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_d16_xy:
; UNPACKED: s_load_dwordx2 s[[[S_DATA:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], s[[S_DATA]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], s[[S_DATA]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
; UNPACKED: buffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %index) {
; UNPACKED-LABEL: buffer_store_format_d16_xy:
; UNPACKED: ; %bb.0: ; %main_body
; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; UNPACKED-NEXT: s_lshr_b32 s6, s4, 16
; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
; UNPACKED-NEXT: v_mov_b32_e32 v1, s6
; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; UNPACKED-NEXT: buffer_store_format_d16_xy v[0:1], v2, s[0:3], 0 idxen
; UNPACKED-NEXT: s_endpgm
;
; PACKED-LABEL: buffer_store_format_d16_xy:
; PACKED: ; %bb.0: ; %main_body
; PACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; PACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-NEXT: v_mov_b32_e32 v0, s4
; PACKED-NEXT: v_mov_b32_e32 v1, s5
; PACKED-NEXT: buffer_store_format_d16_xy v0, v1, s[0:3], 0 idxen
; PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.buffer.store.format.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_d16_xyz:
; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
; UNPACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
; PACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xyz(<4 x i32> %rsrc, <4 x half> %data, i32 %index) {
; UNPACKED-LABEL: buffer_store_format_d16_xyz:
; UNPACKED: ; %bb.0: ; %main_body
; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; UNPACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
; UNPACKED-NEXT: s_lshr_b32 s7, s4, 16
; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
; UNPACKED-NEXT: v_mov_b32_e32 v1, s7
; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; UNPACKED-NEXT: v_mov_b32_e32 v3, s6
; UNPACKED-NEXT: buffer_store_format_d16_xyz v[0:2], v3, s[0:3], 0 idxen
; UNPACKED-NEXT: s_endpgm
;
; PACKED-LABEL: buffer_store_format_d16_xyz:
; PACKED: ; %bb.0: ; %main_body
; PACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; PACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; PACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-NEXT: s_and_b32 s5, s5, 0xffff
; PACKED-NEXT: v_mov_b32_e32 v0, s4
; PACKED-NEXT: v_mov_b32_e32 v1, s5
; PACKED-NEXT: v_mov_b32_e32 v2, s6
; PACKED-NEXT: buffer_store_format_d16_xyz v[0:1], v2, s[0:3], 0 idxen
; PACKED-NEXT: s_endpgm
main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> poison, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.struct.buffer.store.format.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw:
; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; UNPACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
; PACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %index) {
; UNPACKED-LABEL: buffer_store_format_d16_xyzw:
; UNPACKED: ; %bb.0: ; %main_body
; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; UNPACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; UNPACKED-NEXT: s_lshr_b32 s7, s5, 16
; UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
; UNPACKED-NEXT: s_lshr_b32 s8, s4, 16
; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
; UNPACKED-NEXT: v_mov_b32_e32 v1, s8
; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; UNPACKED-NEXT: v_mov_b32_e32 v3, s7
; UNPACKED-NEXT: v_mov_b32_e32 v4, s6
; UNPACKED-NEXT: buffer_store_format_d16_xyzw v[0:3], v4, s[0:3], 0 idxen
; UNPACKED-NEXT: s_endpgm
;
; PACKED-LABEL: buffer_store_format_d16_xyzw:
; PACKED: ; %bb.0: ; %main_body
; PACKED-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; PACKED-NEXT: s_load_dword s6, s[8:9], 0x18
; PACKED-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-NEXT: v_mov_b32_e32 v0, s4
; PACKED-NEXT: v_mov_b32_e32 v1, s5
; PACKED-NEXT: v_mov_b32_e32 v2, s6
; PACKED-NEXT: buffer_store_format_d16_xyzw v[0:1], v2, s[0:3], 0 idxen
; PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
; GCN-LABEL: {{^}}buffer_store_format_i16_x:
; GCN: s_load_dword s[[LO:[0-9]+]]
; GCN: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[LO]]
; GCN: buffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_i16_x(<4 x i32> %rsrc, [8 x i32], i16 %data, [8 x i32], i32 %index) {
; GCN-LABEL: buffer_store_format_i16_x:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_load_dword s4, s[8:9], 0x30
; GCN-NEXT: s_load_dword s5, s[8:9], 0x54
; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: buffer_store_format_d16_x v0, v1, s[0:3], 0 idxen
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.buffer.store.format.i16(i16 %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void

7452
llvm/test/CodeGen/AMDGPU/scratch-simple.ll
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