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[AArch64] Add aliases for processors apple-a18/s6..10. (#127152)

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apple-a18 is an alias of apple-m4.
apple-s6/s7/s8 are aliases of apple-a13.
apple-s9/s10 are aliases of apple-a16.

As with some other aliases today, this reflects identical ISA feature
support, but not necessarily identical microarchitectures and
performance characteristics.
This commit is contained in:
Ahmed Bougacha
2025-02-17 11:18:45 -08:00
committed by GitHub
parent 15944056aa
commit f0e39c45df
4 changed files with 30 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
clang/test/Driver/print-supported-cpus-aarch64.c
View File

@@ -14,6 +14,7 @@
// CHECK: apple-a15
// CHECK: apple-a16
// CHECK: apple-a17
// CHECK: apple-a18
// CHECK: apple-a7
// CHECK: apple-a8
// CHECK: apple-a9
@@ -21,7 +22,12 @@
// CHECK: apple-m2
// CHECK: apple-m3
// CHECK: apple-m4
// CHECK: apple-s10
// CHECK: apple-s4
// CHECK: apple-s5
// CHECK: apple-s6
// CHECK: apple-s7
// CHECK: apple-s8
// CHECK: apple-s9
// CHECK: Use -mcpu or -mtune to specify the target's processor.

6
clang/test/Misc/target-invalid-cpu-note/aarch64.c
View File

@@ -19,6 +19,7 @@
// CHECK-SAME: {{^}}, apple-a15
// CHECK-SAME: {{^}}, apple-a16
// CHECK-SAME: {{^}}, apple-a17
// CHECK-SAME: {{^}}, apple-a18
// CHECK-SAME: {{^}}, apple-a7
// CHECK-SAME: {{^}}, apple-a8
// CHECK-SAME: {{^}}, apple-a9
@@ -26,8 +27,13 @@
// CHECK-SAME: {{^}}, apple-m2
// CHECK-SAME: {{^}}, apple-m3
// CHECK-SAME: {{^}}, apple-m4
// CHECK-SAME: {{^}}, apple-s10
// CHECK-SAME: {{^}}, apple-s4
// CHECK-SAME: {{^}}, apple-s5
// CHECK-SAME: {{^}}, apple-s6
// CHECK-SAME: {{^}}, apple-s7
// CHECK-SAME: {{^}}, apple-s8
// CHECK-SAME: {{^}}, apple-s9
// CHECK-SAME: {{^}}, carmel
// CHECK-SAME: {{^}}, cobalt-100
// CHECK-SAME: {{^}}, cortex-a34

6
llvm/lib/Target/AArch64/AArch64Processors.td
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@@ -1224,6 +1224,9 @@ def : ProcessorAlias<"apple-s5", "apple-a12">;
def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
[TuneAppleA13]>;
def : ProcessorAlias<"apple-s6", "apple-a13">;
def : ProcessorAlias<"apple-s7", "apple-a13">;
def : ProcessorAlias<"apple-s8", "apple-a13">;
def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
[TuneAppleA14]>;
@@ -1236,12 +1239,15 @@ def : ProcessorAlias<"apple-m2", "apple-a15">;
def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16,
[TuneAppleA16]>;
def : ProcessorAlias<"apple-m3", "apple-a16">;
def : ProcessorAlias<"apple-s9", "apple-a16">;
def : ProcessorAlias<"apple-s10", "apple-a16">;
def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17,
[TuneAppleA17]>;
def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4,
[TuneAppleM4]>;
def : ProcessorAlias<"apple-a18", "apple-m4">;
// Alias for the latest Apple processor model supported by LLVM.
def : ProcessorAlias<"apple-latest", "apple-m4">;

14
llvm/unittests/TargetParser/TargetParserTest.cpp
View File

@@ -1130,14 +1130,20 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUTestParams("apple-s4", "armv8.3-a"),
AArch64CPUTestParams("apple-s5", "armv8.3-a"),
AArch64CPUTestParams("apple-a13", "armv8.4-a"),
AArch64CPUTestParams("apple-s6", "armv8.4-a"),
AArch64CPUTestParams("apple-s7", "armv8.4-a"),
AArch64CPUTestParams("apple-s8", "armv8.4-a"),
AArch64CPUTestParams("apple-a14", "armv8.4-a"),
AArch64CPUTestParams("apple-m1", "armv8.4-a"),
AArch64CPUTestParams("apple-a15", "armv8.6-a"),
AArch64CPUTestParams("apple-m2", "armv8.6-a"),
AArch64CPUTestParams("apple-a16", "armv8.6-a"),
AArch64CPUTestParams("apple-m3", "armv8.6-a"),
AArch64CPUTestParams("apple-s9", "armv8.6-a"),
AArch64CPUTestParams("apple-s10", "armv8.6-a"),
AArch64CPUTestParams("apple-a17", "armv8.6-a"),
AArch64CPUTestParams("apple-m4", "armv8.7-a"),
AArch64CPUTestParams("apple-a18", "armv8.7-a"),
AArch64CPUTestParams("exynos-m3", "armv8-a"),
AArch64CPUTestParams("exynos-m4", "armv8.2-a"),
AArch64CPUTestParams("exynos-m5", "armv8.2-a"),
@@ -1246,13 +1252,17 @@ INSTANTIATE_TEST_SUITE_P(
"apple-a8", "apple-a9"}),
AArch64CPUAliasTestParams({"apple-a12", "apple-s4",
"apple-s5"}),
AArch64CPUAliasTestParams({"apple-a13", "apple-s6",
"apple-s7", "apple-s8"}),
AArch64CPUAliasTestParams({"apple-a14", "apple-m1"}),
AArch64CPUAliasTestParams({"apple-a15", "apple-m2"}),
AArch64CPUAliasTestParams({"apple-a16", "apple-m3"})),
AArch64CPUAliasTestParams({"apple-a16", "apple-m3",
"apple-s9", "apple-s10"}),
AArch64CPUAliasTestParams({"apple-m4", "apple-a18"})),
AArch64CPUAliasTestParams::PrintToStringParamName);
// Note: number of CPUs includes aliases.
static constexpr unsigned NumAArch64CPUArchs = 82;
static constexpr unsigned NumAArch64CPUArchs = 88;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;