MC: Adjust -show-inst output for MCExpr
This dump feature does not pass MCAsmInfo to the printer function. When we remove MCSpecifierExpr subclasses (and the printImpl overrides), we will not be able to print target-specific specifier strings. Just print a textual representation.
This commit is contained in:
Fangrui Song
@@ -173,10 +173,15 @@ void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI,
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return;
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}
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case MCExpr::Specifier:
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// TODO: Remove after all targets that use MCSpecifierExpr migrate to
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// MCAsmInfo::printSpecifierExpr.
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return cast<MCSpecifierExpr>(this)->printImpl(OS, MAI);
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case MCExpr::Specifier: {
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auto &SE = cast<MCSpecifierExpr>(*this);
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if (MAI)
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return MAI->printSpecifierExpr(OS, SE);
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// Used by dump features like -show-inst. Regular MCAsmStreamer output must
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// set MAI.
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OS << "specifier(" << SE.getSpecifier() << ',' << *SE.getSubExpr() << ')';
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return;
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}
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}
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llvm_unreachable("Invalid expression kind!");
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@@ -35,7 +35,7 @@ void MCOperand::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const {
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else if (isDFPImm())
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OS << "DFPImm:" << bit_cast<double>(getDFPImm());
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else if (isExpr()) {
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OS << "Expr:(" << *getExpr() << ")";
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OS << "Expr:" << *getExpr();
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} else if (isInst()) {
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OS << "Inst:(";
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if (const auto *Inst = getInst())
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@@ -38,189 +38,189 @@
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define i32 @test1(float %t) {
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; M32-LABEL: test1:
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; M32: # %bb.0: # %entry
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; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
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; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
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; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
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; M32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
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; M32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
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; M32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
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; M32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
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; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
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; M32-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
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; M32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
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;
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; M32R2-FP64-LABEL: test1:
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; M32R2-FP64: # %bb.0: # %entry
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; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
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; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
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; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
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; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
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; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
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; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
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; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
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; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
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; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
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; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
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;
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; M32R2-SF-LABEL: test1:
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; M32R2-SF: # %bb.0: # %entry
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; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
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; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
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; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
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; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: # <MCInst #[[#MCINST5:]] SW
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
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; M32R2-SF-NEXT: # <MCOperand Imm:20>>
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; M32R2-SF-NEXT: .cfi_offset 31, -4
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; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL
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; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
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; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #[[#MCINST6:]] JAL
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; M32R2-SF-NEXT: # <MCOperand Expr:__fixsfsi>>
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; M32R2-SF-NEXT: nop # <MCInst #[[#MCINST7:]] SLL
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6:]]>
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
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; M32R2-SF-NEXT: # <MCOperand Imm:0>>
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; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: # <MCInst #[[#MCINST8:]] LW
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
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; M32R2-SF-NEXT: # <MCOperand Imm:20>>
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; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R2-SF-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
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; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
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; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
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; M32R2-SF-NEXT: # <MCOperand Imm:24>>
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;
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; M32R3R5-LABEL: test1:
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; M32R3R5: # %bb.0: # %entry
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; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
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; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
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; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
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; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
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; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
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; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
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; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
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; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
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; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
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; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
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;
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; M32R6-LABEL: test1:
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; M32R6: # %bb.0: # %entry
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; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
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; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
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; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
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; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
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; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
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; M32R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
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; M32R6-NEXT: jr $ra # <MCInst #[[#MCINST9:]] JALR
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; M32R6-NEXT: # <MCOperand Reg:[[#MCREG6:]]>
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; M32R6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
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; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
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; M32R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
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; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
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;
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; M64-LABEL: test1:
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; M64: # %bb.0: # %entry
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; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
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; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
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; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
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; M64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
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; M64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
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; M64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
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; M64-NEXT: # <MCOperand Reg:[[#MCREG7:]]>>
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; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
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; M64-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
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; M64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
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;
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; M64R6-LABEL: test1:
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; M64R6: # %bb.0: # %entry
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; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
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; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
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; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
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; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
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; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
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; M64R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
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; M64R6-NEXT: jr $ra # <MCInst #[[#MCINST10:]] JALR64
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; M64R6-NEXT: # <MCOperand Reg:[[#MCREG8:]]>
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; M64R6-NEXT: # <MCOperand Reg:[[#MCREG7:]]>>
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; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
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; M64R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
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; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
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;
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; MMR2-FP32-LABEL: test1:
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; MMR2-FP32: # %bb.0: # %entry
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; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
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; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-FP32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
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; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
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; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST11:]] TRUNC_W_S_MM
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; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
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; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
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; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
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; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
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; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
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; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
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; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
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;
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; MMR2-FP64-LABEL: test1:
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; MMR2-FP64: # %bb.0: # %entry
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; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
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; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
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; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
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; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST11:]] TRUNC_W_S_MM
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; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
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; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
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; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
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; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
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; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
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; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
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; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
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;
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; MMR2-SF-LABEL: test1:
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; MMR2-SF: # %bb.0: # %entry
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; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
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; MMR2-SF-NEXT: addiusp -24 # <MCInst #[[#MCINST14:]] ADDIUSP_MM
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; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
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; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
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; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
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; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-SF-NEXT: # <MCInst #[[#MCINST15:]] SWSP_MM
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; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
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; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
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; MMR2-SF-NEXT: # <MCOperand Imm:20>>
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; MMR2-SF-NEXT: .cfi_offset 31, -4
|
||||
; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
|
||||
; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #[[#MCINST16:]] JAL_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Expr:__fixsfsi>>
|
||||
; MMR2-SF-NEXT: nop # <MCInst #[[#MCINST17:]] SLL_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6:]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:0>>
|
||||
; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: # <MCInst #[[#MCINST18:]] LWSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
|
||||
; MMR2-SF-NEXT: addiusp 24 # <MCInst #[[#MCINST14]] ADDIUSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:24>>
|
||||
; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR2-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
;
|
||||
; MMR6-LABEL: test1:
|
||||
; MMR6: # %bb.0: # %entry
|
||||
; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MMR6
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST20:]] TRUNC_W_S_MMR6
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
|
||||
; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
|
||||
;
|
||||
; MMR6-SF-LABEL: test1:
|
||||
; MMR6-SF: # %bb.0: # %entry
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
|
||||
; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
|
||||
; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCInst #[[#MCINST5:]] SW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR6-SF-NEXT: .cfi_offset 31, -4
|
||||
; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #{{[0-9]+}} BALC_MMR6
|
||||
; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
|
||||
; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #[[#MCINST21:]] BALC_MMR6
|
||||
; MMR6-SF-NEXT: # <MCOperand Expr:__fixsfsi>>
|
||||
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCInst #[[#MCINST8:]] LW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:24>>
|
||||
; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR6-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
entry:
|
||||
%conv = fptosi float %t to i32
|
||||
ret i32 %conv
|
||||
@@ -229,189 +229,189 @@ entry:
|
||||
define i32 @test2(double %t) {
|
||||
; M32-LABEL: test2:
|
||||
; M32: # %bb.0: # %entry
|
||||
; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
|
||||
; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
|
||||
; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST22:]] TRUNC_W_D32
|
||||
; M32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
|
||||
; M32-NEXT: # <MCOperand Reg:[[#MCREG9:]]>>
|
||||
; M32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
|
||||
; M32-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
|
||||
; M32-NEXT: # <MCOperand Reg:[[#MCREG4]]>
|
||||
; M32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
;
|
||||
; M32R2-FP64-LABEL: test2:
|
||||
; M32R2-FP64: # %bb.0: # %entry
|
||||
; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
|
||||
; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4]]>
|
||||
; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
;
|
||||
; M32R2-SF-LABEL: test2:
|
||||
; M32R2-SF: # %bb.0: # %entry
|
||||
; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4]] ADDiu
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
|
||||
; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
|
||||
; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: # <MCInst #[[#MCINST5]] SW
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; M32R2-SF-NEXT: .cfi_offset 31, -4
|
||||
; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL
|
||||
; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
|
||||
; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #[[#MCINST6]] JAL
|
||||
; M32R2-SF-NEXT: # <MCOperand Expr:__fixdfsi>>
|
||||
; M32R2-SF-NEXT: nop # <MCInst #[[#MCINST7]] SLL
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:0>>
|
||||
; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: # <MCInst #[[#MCINST8]] LW
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R2-SF-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; M32R2-SF-NEXT: # <MCOperand Imm:24>>
|
||||
;
|
||||
; M32R3R5-LABEL: test2:
|
||||
; M32R3R5: # %bb.0: # %entry
|
||||
; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST22:]] TRUNC_W_D32
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1]]>
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG9:]]>>
|
||||
; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG4]]>
|
||||
; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
;
|
||||
; M32R6-LABEL: test2:
|
||||
; M32R6: # %bb.0: # %entry
|
||||
; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
|
||||
; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
|
||||
; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
|
||||
; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
|
||||
; M32R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
|
||||
; M32R6-NEXT: jr $ra # <MCInst #[[#MCINST9]] JALR
|
||||
; M32R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>
|
||||
; M32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
|
||||
; M32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
|
||||
; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
;
|
||||
; M64-LABEL: test2:
|
||||
; M64: # %bb.0: # %entry
|
||||
; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
|
||||
; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
|
||||
; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
|
||||
; M64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
|
||||
; M64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
|
||||
; M64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
|
||||
; M64-NEXT: # <MCOperand Reg:[[#MCREG7]]>>
|
||||
; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
|
||||
; M64-NEXT: # <MCOperand Reg:[[#MCREG4]]>
|
||||
; M64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
;
|
||||
; M64R6-LABEL: test2:
|
||||
; M64R6: # %bb.0: # %entry
|
||||
; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
|
||||
; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
|
||||
; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
|
||||
; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
|
||||
; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
|
||||
; M64R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
|
||||
; M64R6-NEXT: jr $ra # <MCInst #[[#MCINST10]] JALR64
|
||||
; M64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
|
||||
; M64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>>
|
||||
; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
|
||||
; M64R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
|
||||
; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
;
|
||||
; MMR2-FP32-LABEL: test2:
|
||||
; MMR2-FP32: # %bb.0: # %entry
|
||||
; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_MM
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR2-FP32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST24:]] TRUNC_W_MM
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG9:]]>>
|
||||
; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG4]]>
|
||||
; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
;
|
||||
; MMR2-FP64-LABEL: test2:
|
||||
; MMR2-FP64: # %bb.0: # %entry
|
||||
; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #{{[0-9]+}} CVT_W_D64_MM
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #[[#MCINST25:]] CVT_W_D64_MM
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
|
||||
; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4]]>
|
||||
; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
;
|
||||
; MMR2-SF-LABEL: test2:
|
||||
; MMR2-SF: # %bb.0: # %entry
|
||||
; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
|
||||
; MMR2-SF-NEXT: addiusp -24 # <MCInst #[[#MCINST14]] ADDIUSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
|
||||
; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
|
||||
; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: # <MCInst #[[#MCINST15]] SWSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR2-SF-NEXT: .cfi_offset 31, -4
|
||||
; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
|
||||
; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #[[#MCINST16]] JAL_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Expr:__fixdfsi>>
|
||||
; MMR2-SF-NEXT: nop # <MCInst #[[#MCINST17]] SLL_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:0>>
|
||||
; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR2-SF-NEXT: # <MCInst #[[#MCINST18]] LWSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
|
||||
; MMR2-SF-NEXT: addiusp 24 # <MCInst #[[#MCINST14]] ADDIUSP_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Imm:24>>
|
||||
; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR2-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
|
||||
; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
;
|
||||
; MMR6-LABEL: test2:
|
||||
; MMR6: # %bb.0: # %entry
|
||||
; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D_MMR6
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST26:]] TRUNC_W_D_MMR6
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
|
||||
; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
|
||||
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
|
||||
; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
;
|
||||
; MMR6-SF-LABEL: test2:
|
||||
; MMR6-SF: # %bb.0: # %entry
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4]] ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
|
||||
; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
|
||||
; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCInst #[[#MCINST5]] SW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR6-SF-NEXT: .cfi_offset 31, -4
|
||||
; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #{{[0-9]+}} BALC_MMR6
|
||||
; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
|
||||
; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #[[#MCINST21]] BALC_MMR6
|
||||
; MMR6-SF-NEXT: # <MCOperand Expr:__fixdfsi>>
|
||||
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCInst #[[#MCINST8]] LW
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
|
||||
; MMR6-SF-NEXT: # <MCOperand Imm:24>>
|
||||
; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MMR6-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
|
||||
; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
|
||||
entry:
|
||||
%conv = fptosi double %t to i32
|
||||
ret i32 %conv
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -27,14 +27,14 @@ jump2:
|
||||
! CHECK: encoding: [0b1110110A,A,A,0x01'A']
|
||||
! CHECK-NEXT: fixup A - offset: 0, value: jump1, kind: FIXUP_LANAI_25
|
||||
! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
|
||||
! CHECK-NEXT: <MCOperand Expr:(jump1)>
|
||||
! CHECK-NEXT: <MCOperand Expr:specifier(0,jump1)>
|
||||
! CHECK-NEXT: <MCOperand Imm:13>
|
||||
|
||||
bpl jump2
|
||||
! CHECK: encoding: [0b1110101A,A,A,A]
|
||||
! CHECK-NEXT: fixup A - offset: 0, value: jump2, kind: FIXUP_LANAI_25
|
||||
! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
|
||||
! CHECK-NEXT: <MCOperand Expr:(jump2)>
|
||||
! CHECK-NEXT: <MCOperand Expr:specifier(0,jump2)>
|
||||
! CHECK-NEXT: <MCOperand Imm:10>
|
||||
|
||||
bt .
|
||||
@@ -43,7 +43,7 @@ jump2:
|
||||
! CHECK: encoding: [0b1110000A,A,A,A]
|
||||
! CHECK-NEXT: fixup A - offset: 0, value: .Ltmp0, kind: FIXUP_LANAI_25
|
||||
! CHECK-NEXT: <MCInst #{{[0-9]+}} BT{{$}}
|
||||
! CHECK-NEXT: <MCOperand Expr:(.Ltmp0)>
|
||||
! CHECK-NEXT: <MCOperand Expr:.Ltmp0>
|
||||
|
||||
! SCC
|
||||
spl %r19
|
||||
|
||||
@@ -235,7 +235,7 @@
|
||||
! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
|
||||
! CHECK-NEXT: <MCOperand Reg:11>
|
||||
! CHECK-NEXT: <MCOperand Reg:7>
|
||||
! CHECK-NEXT: <MCOperand Expr:(hi(x))>
|
||||
! CHECK-NEXT: <MCOperand Expr:specifier(1,x)>
|
||||
|
||||
mov hi(l+4), %r7
|
||||
! CHECK: encoding: [0x03,0x81,A,A]
|
||||
@@ -243,5 +243,5 @@
|
||||
! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
|
||||
! CHECK-NEXT: <MCOperand Reg:14>
|
||||
! CHECK-NEXT: <MCOperand Reg:7>
|
||||
! CHECK-NEXT: <MCOperand Expr:(hi(l)+4)>
|
||||
! CHECK-NEXT: <MCOperand Expr:specifier(1,l)+4>
|
||||
|
||||
|
||||
Reference in New Issue
Block a user