Commit Graph

542019 Commits

Author SHA1 Message Date
Pavel Labath
46e1e9f104 Reapply "[lldb/cmake] Plugin layering enforcement mechanism (#144543)" (#145305)
The only difference from the original PR are the added BRIEF and
FULL_DOCS arguments to define_property, which are required for
cmake<3.23.
2025-06-24 11:10:35 +02:00
Diana Picus
a201f8872a [AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget
feature, as requested in #130030.
2025-06-24 11:09:36 +02:00
Lang Hames
6cfa03f1f1 [ORC] Drop unused LinkGraphLinkingLayer::Plugin::notifyLoaded method. (#145457)
This method was included in the original Plugin API as a counterpart to
JITEventListener::notifyLoaded but was never used.
2025-06-24 19:00:24 +10:00
antoine moynault
5fa55b2dfc Revert "[flang][OpenMP] Skip runtime mapping with no offload targets (#144534)" (#145478)
And also revert 6ba1955 "[flang][OpenMP] Fix ignore-target-data.f90 test"

As it causes several bot failures
https://github.com/llvm/llvm-project/pull/144534#issuecomment-2995303224
2025-06-24 10:51:26 +02:00
Matt Arsenault
73e4f8a71f ARM: Use member initializer list (#145459) 2025-06-24 17:47:34 +09:00
Kazu Hirata
8d9911e4a0 [Option] Use a range-based for loop (NFC) (#145446) 2025-06-24 00:46:17 -07:00
Aviad Cohen
d5c8024dae [mlir][bazel]: Add FuncUtil rule in bazel files (#145463) 2025-06-24 10:40:57 +03:00
Nikita Popov
0112f12eb6 [EarlyCSE] Remove void return restriction for call CSE (#145320)
For readonly/readnone calls returning void we can't CSE the return
value. However, making these participate in CSE is still useful,
because it allows DCE of calls that are not willreturn/nounwind
(something no other part of LLVM is capable of removing).

The more interesting use-case is CSE for writeonly calls (not
yet supported), but I figured this change makes sense independently.

There is no impact on compile-time.
2025-06-24 09:20:03 +02:00
Juan Manuel Martinez Caamaño
8ec0552a7f Reapply "[CUDA][HIP] Add a __device__ version of std::__glibcxx_assert_fail() (#144886)
Modifications to reapply the commit:
* Add noexcept only after C++11 on __glibcxx_assert_fail
* Remove vararg version of __glibcxx_assert_fail
2025-06-24 09:13:13 +02:00
Kazu Hirata
f704738781 [verify-uselistorder] Use llvm::is_sorted (NFC) (#145444)
We can pass a range to llvm::is_sorted.
2025-06-24 00:10:22 -07:00
Antonio Frighetto
1247fddf36 [SimplifyCFG] Relax cttz cost check in simplifySwitchOfPowersOfTwo
We should be able to allow `simplifySwitchOfPowersOfTwo` transform
to take place, as, on recent X86 targets, the weighted latency-size
appears to be 2. This favours computing trailing zeroes and indexing
into a smaller value table, over generating a jump table with an
indirect branch, which overall should be more efficient.
2025-06-24 09:06:18 +02:00
Matthias Springer
c5972da34a [mlir][Transforms] Dialect Conversion: Simplify block-inline handling (#145308)
When a block is getting inlined, the destination block does not have to
be legalized. That's because the signature of the destination block does
not change by inlining.

This commit makes the implementation consistent with this comment:
```
  // If the pattern moved or created any blocks, make sure the types of block
  // arguments get legalized.
```
2025-06-24 08:52:13 +02:00
Fabian Ritter
3e1e368824 [AMDGPU][SDAG] Add tests for ISD::PTRADD DAG combines (#142738)
Pre-committing tests to show improvements in a follow-up PR with the
combines.
2025-06-24 08:43:54 +02:00
Feng Zou
b1dcf78378 [X86][APX] Fix issue of push2/pop2 instr with stack clash protection (#145303)
When -stack-clash-protection option is specified and APX push2pop2 is
enabled, there will be two calls to emitSPUpdate function which emits
two STACKALLOC_W_PROBING pseudo instructions. The pseudo instruction for
push2 padding is silently ignored which leads to the stack misaligned to
16 bytes and GP exception in runtime. Fixed by directly emitting "push
%rax" instruction for push2 padding, instead of calling emitSPUpdate.
There was a similar issue on https://reviews.llvm.org/D150033.
2025-06-24 14:22:14 +08:00
Durgadoss R
ef048471f7 [NVPTX][NFC] Rearrange the TMA-S2G intrinsics (#144903)
This patch moves the TMA S2G intrinsics into their own set of loops.
This is in preparation for adding im2colw/w128 modes support to
the G2S intrinsics (but the S2G ones do not support those modes).

Signed-off-by: Durgadoss R <durgadossr@nvidia.com>
2025-06-24 11:47:21 +05:30
AmirHossein PashaeeHir
b9d1642423 [NFC] Remove UnwindTable dependency on CIE, and FDE (#142520)
This PR is in the direction of separating Unwind table from FDE, and CIE
that depends on llvm/Object.

To separate, first the runtime dependencies have to be removed, which
this commit does that.
This is similar to
[1](https://github.com/llvm/llvm-project/pull/140096),
[2](https://github.com/llvm/llvm-project/pull/139175), and
[3](https://github.com/llvm/llvm-project/pull/139326).
2025-06-23 23:15:18 -07:00
Fangrui Song
290fc1ea11 MC,AsmPrinter: Report redefinition error instead of crashing in more cases
* Fix the crash for `.equiv b, undef; b:` (.equiv equates a symbol to an expression and reports an error if the symbol was already defined).
* Remove redundant isVariable check from emitFunctionEntryLabel

Pull Request: https://github.com/llvm/llvm-project/pull/145460
2025-06-23 23:00:03 -07:00
Nicolas Vasilache
d31ba52563 [mlir][Interface] Factor out common IndexingMapOpInterface behavior in a new generic interface (#145313)
Refactor the verifiers to make use of the common bits and make
`vector.contract` also use this interface.
In the process, the confusingly named getStaticShape has disappeared.

Note: the verifier for IndexingMapOpInterface is currently called
manually from other verifiers as it was unclear how to avoid it taking
precedence over more meaningful error messages
2025-06-24 07:56:32 +02:00
Maksim Panchenko
0c33799e37 [JITLink] Include target addend in out-of-range error (#145423)
When JITLink reports an out-of-range error, the underlying reason could
be hidden from the user if it's due to an excessively large target
addend. Add non-zero target addend to the message for clarity.
2025-06-23 22:46:15 -07:00
Baranov Victor
e435558ff9 [clang-tidy] add 'IgnoreMarcos' option to 'special-member-functions' check (#143550) 2025-06-24 08:39:05 +03:00
Krzysztof Drewniak
5ce5ed4b85 [mlir] Allow using non-attribute properties in declarative rewrite patterns (#143071)
This commit adds support for non-attribute properties (such as
StringProp and I64Prop) in declarative rewrite patterns. The handling
for properties follows the handling for attributes in most cases,
including in the generation of static matchers.

Constraints that are shared between multiple types are supported by
making the constraint matcher a templated function, which is the
equivalent to passing ::mlir::Attribute for an arbitrary C++ type.
2025-06-24 00:20:27 -05:00
Aviad Cohen
f4df9f1c6e [mlir][func]: Fixed linkage problem in func dialect (#145456) 2025-06-24 08:05:05 +03:00
Matt Arsenault
809e2900ff X86: Use reportFatalUsageError for tiny code model error (#145279) 2025-06-24 13:52:30 +09:00
Douglas Yung
ffc7d5ae2d Add REQUIRES: asserts to test added in #145149 because it uses the -debug-only= flag.
This should fix the test failure when building without asserts.
2025-06-24 04:08:34 +00:00
Timm Bäder
0e461d1781 [clang][bytecode] Only use int128 if it is available
This broke a number of buildbots, e.g.
https://lab.llvm.org/buildbot/#/builders/64/builds/4410
2025-06-24 05:53:04 +02:00
Aviad Cohen
3ba7a872bf [mlir][func]: Introduce ReplaceFuncSignature tranform operation (#143381)
This transform takes a module and a function name, and replaces the
signature of the function by reordering the arguments and results
according to the interchange arrays. The function is expected to be
defined in the module, and the interchange arrays must match the number
of arguments and results of the function.
2025-06-24 06:35:06 +03:00
Henrik G. Olsson
37eb465710 Reland "[Modules] Record whether VarDecl initializers contain side effects" (#145447)
This reverts commit 329ae86 and adds an early exit for EvaluateInPlace when the expression's type is null.
2025-06-23 20:20:15 -07:00
Sam Elliott
0fcced7d79 [RISCV][NFC] Zce always implies/requires Zca (#145442) 2025-06-23 20:09:23 -07:00
Jim Lin
f6ab1f02ec [RISCV] Support LLVM IR intrinsics for XAndesVBFHCvt (#145321)
This patch adds LLVM IR intrinsic support for XAndesVBFHCvt.

The document for the intrinsics can be found at:
https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/intrinsic_funcs.adoc#vector-widening-convert-intrinsicsxandesvbfhcvt
https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/intrinsic_funcs.adoc#vector-narrowing-convert-intrinsicsxandesvbfhcvt

Vector bf16 load/store intrisics is also enabled when +xandesvbfhcvt is
specified. The corresponding LLVM IR intrisic testcase would be added in
a follow-up patches.

The clang part will be added in a later patch.

Co-authored-by: Tony Chuan-Yue Yuan <yuan593@andestech.com>
2025-06-24 10:19:04 +08:00
Matt Arsenault
f0d898f36b DAG: Move get_dynamic_area_offset type check to IR verifier (#145268)
Also fix the LangRef to match the implementation. This was checking
against the alloca address space size rather than the default address
space.

The check was also more permissive than the LangRef. The error
check permitted any size less than the pointer size; follow the
stricter wording of the LangRef.
2025-06-24 11:11:52 +09:00
Teresa Johnson
90a6819cfe [MemProf] Update the DISubprogram linkageName for clones (#145385)
This corrects the debug information for the cloned functions so that it
contains the correct linkage name.
2025-06-23 18:57:22 -07:00
Lang Hames
ca04d74564 [ORC] DLLImportDefinitionGenerator should use LookupKind::Static.
LookupKind::DLSym should only be used for lookups issued on behalf of the ORC
runtime's emulated dlsym operation.

This should fix a bug where ORC runtime clients are unable to access functions
exported by the runtime.

https://github.com/llvm/llvm-project/issues/145296
2025-06-24 11:51:32 +10:00
Sudharsan Veeravalli
88b98d3367 [RISCV] Add ISel pattern for generating QC_BREV32 (#145288)
The `QC_BREV32` instruction reverses the bit order of `rs1` and writes
the result to `rd`
2025-06-24 07:11:46 +05:30
yronglin
bd6ee6ac21 [C23][Parser] Accept single variadic parameter function declarator in type name (#145362)
Fixs: https://github.com/llvm/llvm-project/issues/145250.

This PR makes clang accept single variadic parameter function declarator
in type name.
Eg.
```c
int va_fn(...); // ok

// As typeof() argument
typeof(int(...))*fn_ptr = &va_fn;  // ok

// As _Generic association type
int i = _Generic(typeof(va_fn), int(...):1); // ok
```

Signed-off-by: yronglin <yronglin777@gmail.com>
2025-06-24 09:40:01 +08:00
Kazu Hirata
975d4df147 [lldb] Remove an unused local variable (NFC) (#145212) 2025-06-23 18:04:26 -07:00
Kazu Hirata
d4d37d8430 [BOLT] Remove a redundant call to std::unique_ptr<T>::get (NFC) (#145211) 2025-06-23 18:04:19 -07:00
Jim Lin
2f9c97c030 [RISCV] Add Andes AX45MPV processor definition (#145267)
Andes AX45MPV is 64-bit in-order dual-issue 8-stage pipeline
linux-capable CPU implementing the RV64IMAFDCV ISA extension. That is
developed by Andes Technology https://www.andestech.com, a RISC-V IP
provider.

The overviews for AX45MPV:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mpv/

Scheduling model for RVV extension will be implemented a follow-up PR.
2025-06-24 08:57:55 +08:00
Wenju He
9d570d568b [ValueTracking] Return true for AddrSpaceCast in canCreateUndefOrPoison (#144686)
In our downstream GPU target, following IR is valid before instcombine
although the second addrspacecast causes UB.
  define i1 @test(ptr addrspace(1) noundef %v) {
    %0 = addrspacecast ptr addrspace(1) %v to ptr addrspace(4)
    %1 = call i32 @llvm.xxxx.isaddr.shared(ptr addrspace(4) %0)
    %2 = icmp eq i32 %1, 0
    %3 = addrspacecast ptr addrspace(4) %0 to ptr addrspace(3)
    %4 = select i1 %2, ptr addrspace(3) null, ptr addrspace(3) %3
    %5 = icmp eq ptr addrspace(3) %4, null
    ret i1 %5
  }
We have a custom optimization that replaces invalid addrspacecast with
poison, and IR is still valid since `select` stops poison propagation.

However, instcombine pass optimizes `select` to `or`:
    %0 = addrspacecast ptr addrspace(1) %v to ptr addrspace(4)
    %1 = call i32 @llvm.xxxx.isaddr.shared(ptr addrspace(4) %0)
    %2 = icmp eq i32 %1, 0
    %3 = addrspacecast ptr addrspace(1) %v to ptr addrspace(3)
    %4 = icmp eq ptr addrspace(3) %3, null
    %5 = or i1 %2, %4
    ret i1 %5
The transform is invalid for our target.

---------

Co-authored-by: Nikita Popov <github@npopov.com>
2025-06-24 08:43:47 +08:00
Anshil Gandhi
a314ac4d22 [Reland][InstCombine] Iterative replacement in PtrReplacer (#145410)
This patch enhances the PtrReplacer as follows:

1. Users are now collected iteratively to be generous on the stack. In
the case of PHIs with incoming values which have not yet been visited,
they are pushed back into the stack for reconsideration.
2. Replace users of the pointer root in a reverse-postorder traversal,
instead of a simple traversal over the collected users. This reordering
ensures that the uses of an instruction are replaced before replacing
the instruction itself.
3. During the replacement of PHI, use the same incoming value if it does
not have a replacement.

This patch specifically fixes the case when an incoming value of a PHI
is addrspacecasted.

This reland PR includes a fix for an assertion failure caused by
https://github.com/llvm/llvm-project/pull/137215, which was reverted.
The failing test involved a phi and gep depending on each other, in
which case the PtrReplacer did not order them correctly for replacement.
This patch fixes it by adding a check during the definition of
`PostOrderWorklist`.
2025-06-23 20:35:40 -04:00
Finn Plummer
310a62f88a [HLSL][RootSignature] Plug-in serialization and add full sample testcase (#144769)
This pr extends `dumpRootElements` to invoke the print methods of all
`RootElement`s now that they are all implemented.

Extends the `RootSignatures-AST.hlsl` testcase to have a root element of
each type being parsed, constructed to the in-memory representation mode
and then being dumped as part of the AST dump.

- Update `HLSLRootSignatureUtils.cpp` to extend `dumpRootElements`
- Extend `AST/HLSL/RootSigantures-AST.hlsl` testcase
- Defines the helper `operator<<` for `RootElement`
- Small correction to the output of `numDescriptors` to be `unbounded`
in special case

Resolves https://github.com/llvm/llvm-project/issues/124595.
2025-06-23 17:19:12 -07:00
Maksim Levental
a2aa812a31 [mlir][python] bind block predecessors and successors (#145116)
bind `block.getSuccessor` and `block.getPredecessors`.
2025-06-23 19:59:03 -04:00
sribee8
bc5e5c0114 [libc] wcpncpy implementation (#145430)
Implemented wcpncpy and tests.

---------

Co-authored-by: Sriya Pratipati <sriyap@google.com>
2025-06-23 23:35:28 +00:00
sribee8
10d46cf0d5 [libc] mbtowc implementation (#145405)
Implemented mbtowcs and tests for the function.

---------

Co-authored-by: Sriya Pratipati <sriyap@google.com>
2025-06-23 23:25:13 +00:00
Prajwal Nadig
23b66a68f1 [ExtractAPI] Include virtual keyword for methods (#145412)
This information was being left out of the symbol graph.

rdar://131780883
2025-06-23 17:10:43 -06:00
Paul Osmialowski
4b9f7cd856 [flang] flang manpage overhaul (#144948)
Make the flang man page look more like the one clang is having.
2025-06-24 00:07:10 +01:00
Shubh Pachchigar
98e8ef2273 [libc] Fix broken links in libc (#145199)
This PR fixes broken links in all files describing libc usage modes.
Please let me know if there are any other places that need updating.

---------

Co-authored-by: shubhp@perlmutter <shubhp@perlmutter.com>
2025-06-23 15:51:43 -07:00
S. VenkataKeerthy
d37325ea95 Revert "[MLGO][IR2Vec] Integrating IR2Vec with MLInliner (#143479)" (#145418)
This reverts commit af2c06ecd6 as it
causes failure of lit test (Transforms/Inline/ML/interactive-mode.ll)
2025-06-24 00:48:16 +02:00
Chelsea Cassanova
92a7f6fbbe [lldb][rpc] Fix bug in convert script for RPC (#145419)
In the script that's used by RPC to convert LLDB headers to LLDB RPC
headers, there's a bug with how it converts namespace usage. An
overeager regex pattern caused *all* text before any `lldb::` namespace
usage to get replaced with `lldb_rpc::` instead of just the namespace
itself. This commit changes that regex pattern to be less overeager and
modifies one of the shell tests for this script to actually check that
the namespace usage replacement is working correctly.

rdar://154126268
2025-06-23 15:46:12 -07:00
Aaron St George
3782eb60f8 [mlir][TilingInterface] NFC Improve comment for tiledAndFusedOps member of SCFTileAndFuseResult (#145397)
Comment was a little unclear, hopefully this change is an improvement.
2025-06-23 15:08:42 -07:00
Tex Riddell
509fb931b4 Fix min_vec_size.ll test for changes in vector-combine (#145392)
Running the `vector-combine` pass on this test now produces a single
shuffle on a loaded `<1 x float>` instead of an insert into a `<2 x
float>` followed by a shuffle.

This test change matches changes in other tests in PR #144690, which
introduced the optimization.
2025-06-23 14:53:57 -07:00